Senior ASIC Physical Design Engineer
K2 SpaceJob Title
Senior ASIC Physical Design Engineer
Role Summary
Lead physical design for advanced SoC blocks and top-level integration used in high-power satellite systems. Work across synthesis, place & route, timing closure, and sign-off with front-end, verification, DFT, packaging, and external vendors.
The role focuses on achieving PPA and timing closure for complex mixed-signal SoCs destined for spaceflight, supporting designs through production and tapeout.
Experience Level
Senior — typically 5–10 years of ASIC physical design experience for complex SoCs.
Responsibilities
Execute and own physical design tasks from synthesis through sign-off and support integration to tapeout and production.
- Execute complete physical design flow: synthesis, floorplanning, placement & routing, CTS, STA, and physical verification.
- Perform timing closure and optimization across multiple corners and modes.
- Collaborate with RTL, verification, DFT, and packaging teams to ensure clean handoffs and integration.
- Work with external physical-design service providers to review deliverables and resolve issues.
- Develop and maintain scripts and automation to improve flow efficiency and repeatability.
- Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
- Assist with chip-level ECOs, tapeout preparation, and production support.
- Contribute to methodology development, tool evaluation, and flow documentation.
Requirements
Must-have technical skills and experience required to contribute immediately.
- 5–10 years of ASIC physical design experience on complex SoCs.
- Hands-on experience with industry tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
- Strong understanding of timing analysis, power optimization, and physical verification flows.
- Experience with hierarchical or flat SoC design methodologies and ECO implementation.
- Familiarity with FinFET technologies and UPF/CPF power intent.
- Working knowledge of DFT and ability to collaborate with verification/DFT teams.
- Strong scripting and automation skills to improve design flows.
- Ability to work cross-functionally in a fast-paced environment and support production/spaceflight requirements.
Nice-to-have:
- Experience with radiation-hardened or space-qualified ASICs.
- Chip-package co-design or advanced packaging (2.5D/3D) experience.
- Experience managing physical design service vendors and offshore collaboration.
- Experience with sign-off through major foundries (e.g., TSMC) and Gate-All-Around technologies.
- Experience working with geographically distributed teams.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
About the Company
Company: K2 Space
Headquarters: United States
K2 Space specializes in providing high-quality engineering solutions for ASIC, FPGA, and RTL designs. The company focuses on advanced digital design verification and development, catering to the growing demands of the semiconductor industry.
