Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

Senior physical design engineer responsible for digital back-end (synthesis through verified top-level layout) and physical verification for mixed-signal and digital ASICs in the Miniature Device Technologies Group. The role supports prototype and mission-focused ASICs used in compact, low-power systems for national security applications.

The position works across digital design, verification, and software teams to resolve back-end issues, perform custom layout when needed, and guide process selection and design partitioning toward successful tapeout.

Experience Level

Senior — requires substantial, hands-on ASIC back-end experience; posting specifies 6+ years performing back-end ASIC design.

Responsibilities

Primary responsibilities focus on digital back-end implementation, verification, and mentoring.

• Implement complete digital back-end flow from synthesis to a verified top-level layout ready for tapeout.
• Top-level floorplanning for digital and mixed-signal ASICs and design partitioning to meet timing and area targets.
• Perform timing analysis and drive fixes across RTL and gate-level phases.
• Insert SCAN and BIST for defect coverage and support testability.
• Execute physical verification including DRC, DRC+, MCD, and LVS using established tools.
• Perform custom physical layout and make top-level custom modifications as required.
• Support process selection for new proposals by assessing size, power, available features, and IP.
• Debug back-end related issues in coordination with digital designers and verification teams.
• Contribute to environment improvements and scripting to streamline flows.
• Provide leadership and mentoring to junior physical design engineers and collaborate across teams to meet project goals.

Requirements

Must-have technical skills, experience, and eligibility for a U.S. government clearance.

• 6+ years of direct, hands-on back-end ASIC design experience.
• Proficiency with Cadence back-end ASIC design tools for implementation.
• Proficiency with Siemens Calibre physical verification tools (DRC/LVS/MCD workflows).
• Experience with synthesis, floorplanning, timing analysis, SCAN/BIST insertion, and design partitioning for timing closure.
• Ability to perform custom physical layout and top-level custom modifications.
• Ability to obtain an Interim Secret security clearance by start and ultimately a Secret clearance; U.S. citizenship required.

Nice-to-have:

• Experience with Cadence Virtuoso for custom layout.
• Experience with Siemens ASIC design toolchains for back-end flow.
• Extensive experience in ASIC technology characterization for process selection.
• Active security clearance or prior single-scope background investigation.

Education Requirements

Associate's degree in a technical field, or equivalent combination of education, experience, and/or certifications is acceptable per the posting. (The posting permits equivalent practical experience in lieu of a degree.)

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.