Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

Join the Common Hardware Group to drive RTL-to-GDSII implementation for advanced networking ASICs. You'll own floorplanning, place-and-route, timing and power strategies, and work across RTL, DFT, EDA vendors, and tool teams to deliver high-performance chips.

Experience Level

Senior. Hiring expects experienced ASIC physical designers; minimum qualifications outline year-guidance tied to degree (see Education Requirements).

Responsibilities

Primary responsibilities include full-chip physical implementation and improving backend flows.

• Lead RTL-to-GDSII implementation for advanced process nodes (sub-16nm to 3nm).
• Define and execute hierarchical floorplanning, placement, routing, clock distribution, and power-grid strategies.
• Drive timing convergence: static timing analysis (STA), setup reviews, multi-mode/multi-corner sign-offs.
• Develop and maintain timing ECO strategies and automation (e.g., Tweaker/PrimeTime flows).
• Analyze quality and efficiency gaps; recommend and implement tool, flow, and methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to resolve issues and align methodology.
• Evaluate and introduce new timing methodologies and provide creative debugging solutions.
• Contribute to best practices and drive methodology alignment across projects.

Requirements

Must-have technical skills and experience for successful performance in this role. Education degree details are summarized separately in Education Requirements.

• Proven ASIC physical design experience, including full-chip activities such as floor-planning, partitioning, pin-assignment, and power-grid planning.
• Hands-on experience with EDA tools such as Innovus, Tempus/PrimeTime, Redhawk/Voltus, Calibre/Pegasus (or equivalent).
• Strong expertise in static timing analysis, constraint definition, timing closure, and multi-corner/multi-mode verification.
• Experience implementing timing ECOs and sign-off flows; ability to script and automate STA tasks.
• Knowledge of hierarchical design flows and physical convergence techniques; familiarity with chip-level clocking (H-tree or mesh) is beneficial.
• Ability to analyze power integrity and interact with power analysis tools and teams.
• Proficiency in scripting (Python preferred) and ability to build automation; familiarity with using AI tools for tooling/programming support is a plus.
• Strong cross-functional communication skills and experience coordinating with RTL, DFT, and EDA vendor teams.

Education Requirements

Minimum qualifications specify one of: Bachelor’s degree in Electrical or Computer Engineering plus 7+ years ASIC experience; Master’s degree in Electrical or Computer Engineering plus 4+ years ASIC experience; or PhD in Electrical or Computer Engineering plus 1+ year ASIC experience. (Degrees and years are explicit requirements in the posting.)

About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).