Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

Own end-to-end physical implementation of high-performance interface IPs and test chips at advanced process nodes, taking designs from RTL through synthesis, placement, routing and signoff. Work on implementation flows, automation and cross-functional integration with front-end, DFT and verification teams.

This role focuses on delivering tape-out-quality implementations, improving methodology, and reducing silicon respins through rigorous timing, power and physical verification practices.

Experience Level

Mid-level — 3 to 5 years of hands-on ASIC physical implementation experience.

Responsibilities

Primary responsibilities include owning implementation tasks and improving team productivity through flows and automation.

• Lead RTL-to-GDS physical implementation: synthesis, floorplanning, placement, CTS, routing and signoff.
• Develop and refine timing constraints; perform static timing analysis and close timing across multiple corners and modes.
• Execute power planning and perform EM/IR analysis to ensure power integrity and reliability signoff.
• Perform physical verification (ICV) to resolve DRC/LVS issues and coordinate with foundry teams for manufacturability.
• Build and improve CAD methodologies and implementation flows using scripting to automate repetitive tasks.
• Collaborate with front-end design, DFT and verification teams to resolve design issues and optimize area, power and performance.
• Support subsystem-level integration and hierarchical implementation across multiple IP blocks.

Requirements

Must-have technical skills and experience.

• 3 to 5 years of hands-on ASIC physical implementation experience with at least one recent tape-out.
• Practical experience with Synopsys tools: Design Compiler, ICC2 or Fusion Compiler, PrimeTime, Star-RCXT, ICV, and RedHawk.
• Experience with deep sub-micron design challenges and signoff at 16nm or below: timing closure, power integrity, EM/IR analysis, and physical verification.
• Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow development.
• Familiarity with timing constraint development, multi-mode multi-corner analysis, and signoff methodologies.
• Strong debugging and communication skills to explain timing/IR issues to cross-functional teams.

Nice-to-have:

• Experience with IP subsystem implementation and hierarchical design flows.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, VLSI Design, or an equivalent technical field; or equivalent practical experience.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.