Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

Senior physical-design engineer in the Miniature Device Technologies Group at Johns Hopkins APL. Responsible for digital back-end flow and top-level physical implementation of mixed-signal and digital ASICs used in small, low-power systems for national security applications.

Experience Level

Senior — requires 6+ years of hands-on back-end ASIC design experience.

Responsibilities

Deliver complete, verified top-level ASIC layouts and support the back-end design flow.

• Implement digital back-end flow from synthesis through timing closure and tapeout-ready top-level layout.
• Top-level floorplanning and design partitioning for timing, power, and area goals.
• Perform timing analysis and closure at RTL and gate-level.
• Insert SCAN and BIST to maximize defect coverage.
• Perform physical verification including DRC, LVS, MCD, and DRC+ using foundry tools.
• Perform custom physical layout and top-level custom modifications as needed.
• Debug back-end issues with digital designers and support fixes in RTL and gate-level flows.
• Contribute to process selection and ASIC technology characterization for new designs.
• Drive tooling/environment improvements and develop scripts to streamline flows.
• Mentor junior physical-design engineers and collaborate across design, verification, and software teams.

Requirements

Must-have technical skills, security eligibility, and relevant experience.

• 6+ years of specific experience performing back-end ASIC design (synthesis, place-and-route, timing closure, signoff).
• Proficient with Cadence back-end design tools for flow implementation.
• Proficient with Siemens Calibre physical verification tools (DRC/LVS/MCD/DRC+).
• Experience with SCAN and BIST insertion and related test methodologies.
• Ability to obtain an Interim Secret security clearance by start date and ultimately a Secret clearance; U.S. citizenship is required for clearance eligibility.

Nice-to-have:

• Experience with custom layout in Cadence Virtuoso.
• Familiarity with Siemens ASIC design toolchain for back-end flow.
• Extensive knowledge of ASIC technology characterization for process selection.
• Active security clearance or prior single-scope background investigation.

Education Requirements

Associate's degree in a technical field, or an equivalent combination of experience, education, and/or certifications is acceptable.

About the Company

Company: Johns Hopkins Applied Physics Laboratory

Headquarters: Laurel, Maryland, United States

Johns Hopkins Applied Physics Laboratory is a nonprofit, university-affiliated research center that develops advanced engineering, science, and technology solutions for national security, space, and government-sponsored missions.