Senior ASIC Physical Design Engineer

Job Title

Senior ASIC Physical Design Engineer

Role Summary

Lead physical design for next-generation AECG ASICs, driving power, performance and area (PPA) targets and delivering RTL-to-GDSII implementations for high-performance products. Collaborate with customers, SoC architects, CAD and design teams to define floorplans and physical design flows.

Hands-on role focused on flow development, automation, problem decomposition, and delivery of signoff-quality ASICs.

Experience Level

Senior — typically 8+ years of professional experience in ASIC physical design (as stated in the posting).

Responsibilities

Primary responsibilities cover end-to-end physical implementation and flow ownership for large ASICs.

• Lead RTL-to-GDSII implementation: floorplanning, power-plan implementation, synthesis, placement, clock tree synthesis, timing closure, routing, extraction, and signoff.
• Drive full-chip floorplanning, bus/pin planning, feed-thru planning, and clock/power architecture decisions.
• Perform static timing analysis, parasitic extraction, physical verification (DRC/LVS), crosstalk analysis, and EM/IR analysis.
• Develop, maintain, and automate P&R flows and scripts; integrate and validate CAD toolchains.
• Collaborate with customers, SoC architects, CAD and design teams to meet PPA and schedule targets.
• Identify complex technical problems, evaluate multiple solutions, and drive implementation to closure.

Requirements

Minimum technical and professional qualifications for the role.

Must-have:

• Proven hands-on physical design and timing expertise covering RTL-to-GDS implementation and signoff.
• Experience with synthesis, timing-driven place-and-route, CTS, routing, parasitic extraction, STA, and physical verification flows.
• Proficiency with industry tools (examples: Synopsys Fusion Compiler/Design Compiler, ICC2/Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache RedHawk, Cadence Genus); comfortable using multiple PNR toolchains.
• Ability to develop and maintain automation scripts and drive flow development.
• Experience optimizing designs for performance, power, and area and reducing design cycle time.
• Strong analytical, problem-solving, organizational and communication skills; able to work across geographically distributed teams.

Nice-to-have:

• Experience with high-speed datapath and control-logic synthesis and P&R.
• Experience with clock/power gating techniques, scan stitching, and automated synthesis flows.
• Familiarity with schematics, layout tools, and circuit/logic simulation.
• Prior experience delivering large IP or SOC blocks to final signoff.
• Experience with FinFET and dual-patterning process nodes (16/14/10/7/5nm).

Education Requirements

BS or MS in Electrical Engineering or Computer Science (or equivalent). The posting also specifies approximately 8+ years of experience in physical design leading RTL-to-GDS development.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.