Senior ASIC Package Design Engineer

Job Title

Senior ASIC Package Design Engineer

Role Summary

Design and deliver advanced ASIC package architectures (primarily flip-chip BGA and multi-chip module solutions) from early architecture and trade studies through vendor qualification and production ramp. Work cross-functionally with silicon, RF, mechanical, and systems teams to ensure manufacturability, signal/power integrity, thermal performance, and first-pass success for high-pin-count, power-dense ASICs.

Experience Level

Senior - requires significant industry experience; the posting specifies 5+ years of relevant ASIC package design experience.

Responsibilities

Primary responsibilities include package architecture, trade studies, design leadership, vendor management, and production readiness.

• Define ASIC package architectures for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, PDN, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, PI/SI, thermal, manufacturability, and reliability.
• Establish package design standards, methodologies, and best practices.
• Drive detailed FC-BGA designs for high-pin-count ASICs with high-speed SerDes and dense power grids.
• Specify and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Collaborate with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces.
• Support SI/PI and EM simulation strategy for high-speed digital interfaces and PDN decoupling.
• Lead package-level thermal architecture, including lid selection, TIMs, heat spreaders, and mechanical thermal interfaces.
• Manage relationships with external packaging vendors, substrate suppliers, and OSATs; drive material and assembly process choices.

Requirements

Must-have technical skills, experience, and hiring constraints.

• 5+ years of ASIC package design experience with deep expertise in FC-BGA.
• Proven track record delivering high-pin-count, high-performance ASIC packages into production.
• Strong understanding of substrate technologies, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs.
• Fluent with SI/PI and EM simulation tools (examples: SIWave, HFSS, ADS).
• Practical experience working directly with OSATs and substrate vendors; knowledge of packaging qualification and test methodologies.
• Ability to support the role's hybrid expectation: in-office presence in Seattle ~3 days per week and periodic travel to Torrance, CA.
• Must meet U.S. export compliance requirements for controlled space technology (ITAR): must be a U.S. person as defined in 22 C.F.R. § 120.15 or otherwise eligible for required authorizations.
• Nice-to-have: experience with MCM/heterogeneous integration (chiplets, interposers), background in high-speed digital or mixed-signal SoCs, and familiarity with aerospace/high-reliability electronics.

Education Requirements

Bachelor's degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field (as stated). The posting does not specify equivalent-experience language beyond the experience requirements.

About the Company

Company: K2 Space

Headquarters: United States

K2 Space specializes in providing high-quality engineering solutions for ASIC, FPGA, and RTL designs. The company focuses on advanced digital design verification and development, catering to the growing demands of the semiconductor industry.