Senior ASIC Package Design Engineer

Job Title

Senior ASIC Package Design Engineer

Role Summary

Lead design and delivery of advanced ASIC package architectures, primarily FC-BGA and multi-chip module (MCM) solutions, from early architecture and trade studies through vendor engagement, qualification, and production ramp.

Collaborate with silicon, RF, systems, and manufacturing teams to define package standards, influence die/package co-optimization, and ensure first-pass success for high-speed, power-dense ASICs.

Experience Level

Senior — typically 5+ years of ASIC package design experience (posting specifies 5+ years).

Responsibilities

Main responsibilities include package architecture definition, trade studies, detailed design, and vendor management.

• Define package architecture for FC-BGA and MCM: substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints.
• Lead package-level trade studies across cost, performance, PI/SI, thermal, manufacturability, and reliability.
• Establish package design standards, methodologies, and best practices.
• Drive detailed FC-BGA design for high-pin-count ASICs with high-speed SerDes and dense power grids.
• Specify substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning.
• Co-optimize die floorplans and package interfaces with silicon, RF, and systems teams.
• Support SI/PI strategy including PDN design and decoupling strategy.
• Lead package-level thermal architecture: lid selection, TIMs, heat spreaders, and mechanical cooling interfaces.
• Drive material selection, substrate technology choices, and assembly process optimization.

Requirements

Must-have skills and experience required for successful performance in this role.

• 5+ years of ASIC package design experience with deep expertise in FC-BGA.
• Proven track record delivering high-pin-count, high-performance ASIC packages into production.
• Strong knowledge of substrate technologies and materials; SI/PI fundamentals at the package level; thermal management for power-dense ASICs.
• Proficiency with SI/PI and EM simulation tools such as SIWave, HFSS, and ADS.
• Experience working directly with OSATs and substrate vendors; familiarity with packaging qualification and test methodologies.
• Ability to lead cross-functional trade studies and define manufacturable package solutions.
• Must be a "U.S. person" or otherwise eligible for required export control authorization per ITAR.

Nice-to-have:

• Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates).
• Background in high-speed digital or mixed-signal SoCs.
• Familiarity with aerospace, space, or high-reliability electronics.

Education Requirements

Bachelor's degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or a related field.

About the Company

Company: K2 Space

Headquarters: United States

K2 Space specializes in providing high-quality engineering solutions for ASIC, FPGA, and RTL designs. The company focuses on advanced digital design verification and development, catering to the growing demands of the semiconductor industry.