Senior ASIC Modelling Engineer

Job Title

Senior ASIC Modelling Engineer

Role Summary

Develop and maintain architectural and performance models for SoC memory infrastructure and client IP. The role focuses on modelling coherency protocols, NoC interconnects, system cache, and memory controllers to guide IP and system-level decisions.

Work with architecture, design, verification and system teams to run exploration campaigns that identify opportunities to improve cost, performance and power across modem, CPU, ML, graphics and multimedia subsystems.

Experience Level

Senior. The posting's minimum qualifications indicate degree-based guidance (see Education Requirements) but candidates with equivalent experience will be considered.

Responsibilities

Primary responsibilities include modelling, analysis, and cross-functional collaboration to drive memory and client IP decisions.

• Develop and validate system-level models of memory subsystems: coherency protocols, NoC fabrics, system caches and memory controllers.
• Implement and maintain models using C++ and SystemC; integrate models into evaluation flows.
• Model client IP behavior (modem, CPU, machine learning, graphics, display, camera, video, peripherals) to assess system impact.
• Plan and execute exploration campaigns to quantify trade-offs in cost, performance, and power.
• Collaborate with cross-functional teams (architects, RTL designers, verification engineers) to inform IP implementation and system decisions.
• Document modelling methodology, assumptions, results, and recommendations; support silicon bring-up and debugging as needed.

Requirements

Skills and domain knowledge required to perform the role; degrees and equivalent-experience rules are listed under Education Requirements.

• Must-have: Proficiency in C++, SystemC, and scripting (e.g., Python, shell).
• Must-have: Practical experience with ASIC modelling, performance analysis, or system-level exploration campaigns.
• Nice-to-have: Knowledge of cache architecture, memory controller architecture, CPU/graphics/multimedia architecture.
• Nice-to-have: Familiarity with on-chip interconnect protocols (AXI, CHI) and RTL design.
• Nice-to-have: Experience with NoC modelling and system cache optimization.

Education Requirements

Minimum qualifications: Bachelor's degree in Science, Engineering, or a related field plus 2+ years of relevant ASIC design/verification/validation/integration experience; OR Master's degree in Science, Engineering, or a related field plus 1+ year of relevant experience; OR PhD in Science or Engineering. The posting states applications from candidates with equivalent experience will be considered.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.