Senior ASIC Engineer
Work on the PMU (power management unit) IP used to optimize chip performance and efficiency for AI datacenter products. The PMU includes a RISC-V core and custom control logic that collect and process chip-wide data to determine operating points.
The role focuses on architecting the next-generation PMU: defining micro-architecture, implementing RTL, and supporting silicon debug in collaboration with software and power architecture teams.
Senior-level role. The posting requests 3+ years of relevant ASIC or system-level design experience.
Primary responsibilities include defining architecture and implementing the PMU micro-architecture, integrating with software and system teams, and supporting silicon bring-up and debug.
Must-have technical skills and experience. Nice-to-have items are listed separately.
Nice-to-have:
BS or MS in Electrical Engineering or Computer Engineering (the posting lists BS/MS in electrical / computer engineering). The posting also states a preference for MS or equivalent practical experience.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
