Senior ASIC Emulation Engineer

Job Title

Senior ASIC Emulation Engineer

Role Summary

As a Senior/Lead ASIC Emulation Engineer you will design, build, and maintain enterprise-scale emulation and FPGA prototyping platforms to verify and validate high-complexity SoCs used in network security products. You will collaborate with architecture, design, verification, firmware, and validation teams to enable pre-silicon bring-up and reproduce post-silicon issues.

Office-based role with an expected in-office cadence of four days per week and one remote day.

Experience Level

Senior-level. The role specifies 8+ years of hands-on experience in hardware emulation, FPGA prototyping, or ASIC verification.

Responsibilities

Key responsibilities include architecting and operating emulation platforms, enabling pre-silicon software bring-up, and debugging complex hardware/firmware failures.

• Architect, bring-up, and maintain Palladium/ZeBu/Veloce-scale emulation platforms and hybrid co-emulation systems.
• Compile, synthesize, and fit large SoC designs onto emulation hardware; perform power, timing, and capacity optimization.
• Develop transactors, rate/speed adapters, and virtual interfaces (C/C++, SystemC, DPI) to integrate emulation with testbenches and traffic generators.
• Execute workloads, benchmarks, and regression suites to enable pre-silicon software and OS/driver bring-up.
• Debug hardware, firmware, and protocol-level failures using waveform captures, dynamic probes, readback, and assertions.
• Automate build, deployment, triage, and regression flows with Python, Tcl, and CI/CD to improve compile speed and platform utilization.
• Collaborate with post-silicon validation to reproduce and triage silicon anomalies on emulation platforms.

Requirements

Must-have technical skills and experience for successful performance.

• 8+ years of hands-on experience in hardware emulation, FPGA prototyping, or ASIC verification with a record of shipping complex SoCs.
• Expertise with at least one emulation platform (Cadence Palladium, Synopsys ZeBu, or Siemens Veloce).
• Strong proficiency in SystemVerilog, Verilog, C/C++, and UVM/DPI interfaces.
• Experience with platform debug tools (SimVision, Indago, Verdi) and advanced emulation debug techniques.
• Experience developing or integrating transactors, speed adapters, and interfaces such as PCIe, Ethernet, DDR, or CXL.
• Advanced scripting and automation skills (Python, Tcl, Perl, UNIX shell) for compilation, regression, and CI/CD workflows.
• Preferred: familiarity with network hardware security architectures, high-speed Ethernet (10G/100G/400G), SystemC/TLM2.0/QEMU integration, driver/firmware debug, and pre-silicon power/thermal analysis tools.

Education Requirements

BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.

About the Company

Company: Palo Alto Networks

Headquarters: Santa Clara, California, United States

Global cybersecurity company that develops network and cloud security products, including next-generation firewalls, endpoint protection, threat intelligence, and AI-driven security platforms for enterprises and service providers.