Senior ASIC DFT Engineer (Silicon)

Job Title

Senior ASIC DFT Engineer (Silicon)

Role Summary

Design and verify Design-for-Test (DFT) architectures and test flows for next-generation ASICs used in space and ground infrastructure. Work with cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, and manufacturing) to enable silicon bring-up, production testing, and yield optimization.

Experience Level

Senior — typically 5+ years of experience in semiconductor DFT engineering, post-silicon validation, or production testing.

Responsibilities

Key responsibilities include defining and executing DFT strategies, developing test patterns and flows, and supporting post-silicon and production test activities.

• Implement and optimize DFT architectures: scan insertion, compression/decompression, memory BIST, and logic BIST (Siemens Tessent workflows).
• Integrate and verify DFT IPs and fabrics within subsystem-level designs.
• Set up and run ATPG tools and methodologies; generate patterns for stuck-at, transition, and path-delay fault models with emphasis on compression, diagnosis, and hierarchical test flows.
• Create and validate DFT patterns for post-silicon bring-up and support ATE debug during silicon characterization.
• Run and debug SDF-annotated gate-level simulations for test validation.
• Develop test scripts and automation for data analysis and flow orchestration using Perl, Python, Tcl, or C++.
• Collaborate with design, verification, and manufacturing teams to ensure testability and production readiness.

Requirements

Must-have qualifications and practical skills for immediate contribution, followed by additional preferred skills.

• 5+ years of hands-on experience in semiconductor DFT engineering, post-silicon validation, or production testing.
• Practical experience with ATPG and pattern generation (stuck-at, transition, path delay); focus on pattern compression and hierarchical flows.
• Experience with scan insertion, compression techniques, memory and logic BIST design/verification.
• Experience supporting post-silicon bring-up and ATE debug for silicon characterization and failure analysis.
• Proficiency in scripting and automation (Perl, Python, Tcl, or C++) for test flow development and data analysis.
• Ability to work extended hours and weekends when required to meet critical milestones.
• Must meet U.S. export-control eligibility (ITAR) requirements to work on this role.

Nice-to-have / Preferred:

• Hands-on experience with Automated Test Equipment platforms (Teradyne, Advantest) and high-volume test development.
• Familiarity with Siemens Tessent tools and Tessent Streaming Scan Network.
• Knowledge of industry testability standards (IEEE 1500, IEEE 1687) and low-power DFT techniques.
• Experience with In-System Test (IST), boundary-scan (IEEE 1149.1), board-level diagnostics, and cell-aware fault models in ATPG.
• Experience in silicon failure analysis, yield optimization, and working at advanced nodes (e.g., 7nm and below).
• Strong problem-solving, documentation, and cross-team communication skills.

Education Requirements

Bachelor's degree required in electrical engineering, computer engineering, or physics. Master's or PhD in electrical engineering, computer engineering, physics, or a related engineering field is preferred.

About the Company

Company: SpaceX

Headquarters: Hawthorne, California, United States

SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.