Senior ASIC DFT/CDC Constraints Engineer

Job Title

Senior ASIC DFT/CDC Constraints Engineer

Role Summary

Senior engineer focused on Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) analysis and ASIC Design-for-Test (DFT) constraints. The role supports the engineering team to maintain design integrity during a transition period and acts as the subject matter expert for CDC/RDC methodology and constraint sign-off.

Remote within the United States; candidate must be available to work in the Pacific (PST) time zone.

Experience Level

Senior — requires at least 10 years of ASIC chip design experience.

Responsibilities

Primary responsibilities include establishing and enforcing CDC/RDC methodology, implementing constraint flows, and validating designs against CDC/RDC and static glitch issues.

• Lead CDC and RDC methodology development and deployment.
• Design and implement RTL with CDC/RDC considerations and best practices.
• Specify comprehensive CDC/RDC check flows and collaborate with CAD to implement them.
• Review and approve CDC/RDC constraints and manage waiver processes.
• Perform static glitch analysis and identify mitigation strategies.
• Improve designs to prevent static glitch hazards and ensure robust timing across domains.
• Support verification activities including SVA checks and simulation as needed.

Requirements

Must-have technical skills and experience for immediate contribution.

• 10+ years of ASIC chip design experience with demonstrated CDC/RDC expertise.
• Proven experience with DFT (Design-for-Test) practices relevant to ASICs.
• Experience maintaining CDC/RDC flows and performing sign-off on constraints and waivers.
• Experience analyzing static glitch hazards on synthesis-optimized gate-level netlists.
• Experience with Static Timing Analysis (STA) and timing closure related to CDC domains.
• Experience with VCS simulation and SystemVerilog Assertions (SVA).
• Ability to work PST hours while located anywhere in the United States.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering (as stated). Degree requirement appears in the source; equivalent experience not specified.

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.