Senior ASIC DFT CDC Constraints Engineer

Job Title

Senior ASIC DFT CDC Constraints Engineer

Role Summary

Senior engineer responsible for CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis, DFT constraint definition, and ensuring design integrity across ASIC projects. Works with RTL designers and CAD to define and maintain CDC/RDC methodology and sign off constraints and waivers.

Experience Level

Senior — requires substantial hands-on ASIC experience. The posting requests at least 10 years of ASIC chip design experience.

Responsibilities

Primary responsibilities include technical leadership of CDC/RDC and DFT constraint activities and delivery of robust, sign-off-ready flows.

• Lead CDC/RDC methodology and implementation across siliconone chips.
• Define and implement reusable RTL patterns and design practices with CDC/RDC considerations.
• Specify comprehensive CDC/RDC check flows and collaborate with CAD to implement and automate them.
• Review and approve CDC/RDC constraints, waiver requests, and sign-off documentation.
• Perform static glitch analysis on synthesis-optimized gate netlists and recommend design fixes.
• Conduct static timing analysis related to multi-domain designs and coordinate fixes with timing teams.
• Use simulation (VCS) and SVA assertions to validate CDC-related behavior and sign-off conditions.
• Act as subject-matter expert to support engineering teams during transitions and design reviews.

Requirements

Core technical skills and constraints for the role. Education details are listed under Education Requirements below.

• Deep practical experience with CDC and RDC analysis and mitigation techniques.
• Hands-on ASIC DFT and constraints experience, including constraint creation and sign-off.
• Experience with static glitch hazard analysis on synthesis-optimized gate-level netlists.
• Proficiency in Static Timing Analysis (STA) and familiarity with timing sign-off processes.
• Experience with simulation and SystemVerilog Assertions (SVA) using VCS or similar tools.
• Ability to define and document check flows; work with CAD/EDA teams to implement automation.
• Strong RTL development experience with CDC-aware coding practices.
• Must be based in the United States and able to work PST business hours.
• Nice-to-have: prior experience creating company-wide CDC/DFT methodology and tool flow integration.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering is requested. The posting specifies at least 10 years of ASIC chip design experience; equivalent practical experience may be considered.

About the Company

Company: CaritaTech

Engineering staffing and consulting firm providing placement and contract services for hardware, semiconductor, and embedded systems professionals, including roles in SoC/ASIC physical design and verification.