Senior ASIC Design Verification Engineer

Job Title

Senior ASIC Design Verification Engineer

Role Summary

Verify functionality, performance, and robustness of custom ASIC/SoC designs for high-power satellite platforms. Work hands-on across the verification flow and partner closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation teams to enable first-generation silicon.

Experience Level

Senior — typically requires 5+ years of ASIC/SoC verification experience.

Responsibilities

Primary responsibilities for the verification engineer include defining and executing verification strategies from block to full-chip, driving regression and coverage closure, and supporting silicon bring-up and post-silicon debug.

• Develop and execute verification plans for block, subsystem, and full-chip levels using SystemVerilog/UVM.
• Implement testbenches: agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and apply formal verification where appropriate.
• Drive constrained-random and directed tests to validate functionality, corner cases, and stress scenarios.
• Run simulations, triage failures, perform root-cause analysis, and work with RTL designers to resolve issues.
• Implement and maintain functional, code, and assertion coverage and work toward coverage closure for sign-off.
• Manage regression suites, simulation infrastructure, and CI pipelines to ensure throughput and fast debug cycles.
• Participate in design and microarchitecture reviews and influence design-for-verification practices.
• Support silicon bring-up, test reuse, diagnostics, and post-silicon validation activities.
• Engage with external IP providers and verification partners as needed.

Requirements

Must-have technical experience and skills for successful performance in this role.

• 5+ years of ASIC/SoC verification experience focused on RTL and verification flows.
• Strong SystemVerilog proficiency and deep understanding of digital logic and RTL design.
• Experience with simulators (e.g., VCS, Xcelium, Questa), waveform debuggers (e.g., Verdi, SimVision), and coverage tools.
• Scripting ability in Python, TCL, Perl, or similar for test automation and tool integration.
• Experience with UVM-based testbench development, constrained-random testing, functional coverage, and SVA.
• Regression management, coverage analysis, revision control (Git), and CI/CD automation experience.
• Familiarity with common interfaces (e.g., APB/AHB/AXI) and embedded processor-based designs with firmware (C/C++).
• Ability to triage failures, perform root-cause analysis, and collaborate across cross-functional teams.
• Must be a U.S. person as required by U.S. export control regulations (ITAR) or eligible for a federal export license.

Nice-to-have

• Experience developing/integrating reference models and low-power verification methodologies.
• Familiarity with gate-level simulation, analog behavioral models, and post-silicon validation planning.
• Experience working on geographically distributed teams and in space, telecom, or RF/mixed-signal systems.

Education Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: K2 Space

Headquarters: United States

K2 Space specializes in providing high-quality engineering solutions for ASIC, FPGA, and RTL designs. The company focuses on advanced digital design verification and development, catering to the growing demands of the semiconductor industry.