Senior ASIC Design Verification Engineer

Job Title

Senior ASIC Design Verification Engineer

Role Summary

Lead verification of next-generation CPU, AI/ML, and SoC designs. Build and maintain UVM/SystemVerilog verification environments, drive functional coverage closure, and collaborate with design and architecture teams from specification through tape-out.

Experience Level

Senior — typically 15+ years of ASIC/SoC verification experience.

Responsibilities

Primary duties include environment development, test execution, RTL debug, and verification signoff.

• Develop UVM/SystemVerilog verification environments, testbenches, sequences, scoreboards, and checkers.
• Create and execute test plans for block-level and full-chip ASIC/SoC verification.
• Perform constrained-random and directed testing and drive functional coverage closure.
• Debug RTL issues and coordinate fixes with design engineers.
• Support regression runs, verification signoff activities, and tape-out readiness.
• Collaborate with design, architecture, and validation teams throughout the project lifecycle.

Requirements

Must-have technical skills and relevant verification experience.

• Must-have:
• SystemVerilog and UVM-based verification experience.
• Constrained-random verification and functional coverage methodologies.
• Strong RTL debug skills and proven ASIC/SoC verification background.
• Nice-to-have:
• CPU/processor or memory-subsystem verification experience; AI/ML accelerator or GPU verification experience.
• SystemVerilog Assertions (SVA) experience.
• Familiarity with simulators and tools such as VCS, Questa, or Xcelium.
• Experience with scripting or programming in Python, C, or C++.

Education Requirements

Bachelor's or Masters degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.

About the Company

Company: VentureSoft Global