Senior ASIC Design Engineer (Silicon Engineering)
SpaceXJob Title
Senior ASIC Design Engineer (Silicon Engineering)
Role Summary
Design and deliver RTL for next-generation ASICs used in SpaceX Starlink space and ground systems. Work on micro-architecture, RTL implementation, verification collaboration, and silicon bring-up with cross-disciplinary teams (architecture, verification, physical implementation, validation).
Focus is on implementing synthesis- and timing-clean designs that meet system performance, power, and reliability requirements for production silicon.
Experience Level
Senior - requires at least 5+ years of experience in RTL implementation and ASIC design.
Responsibilities
Primary responsibilities include translating architecture into RTL, delivering verified RTL to physical implementation, and supporting silicon validation.
- Evaluate architectural trade-offs relative to performance, features, and system constraints.
- Define micro-architecture and implement RTL in Verilog/SystemVerilog; integrate into top-level design.
- Deliver fully verified, synthesis- and timing-clean designs in collaboration with verification teams.
- Provide timing constraints for IP and support synthesis, timing closure, and formal checks with the physical implementation team.
- Participate in silicon bring-up and hardware validation activities.
Requirements
Must-have technical skills and role constraints.
- 5+ years of RTL implementation experience working with Verilog/SystemVerilog.
- Proven ability to produce synthesis- and timing-clean RTL and to work with verification teams to fully verify designs.
- Experience providing timing constraints and supporting synthesis, timing closure, and formality checks.
- Experience with silicon bring-up and hardware validation.
- Must meet U.S. ITAR eligibility (U.S. citizen, lawful permanent resident, refugee, asylee, or eligible to obtain required authorizations).
Nice-to-have / preferred:
- Experience solving clock domain crossing and power-optimization problems.
- ASIC/SoC integration experience and familiarity with embedded CPU subsystems.
- Experience with standard bus protocols (AXI, AHB) and high-speed / low-power design techniques.
- Scripting skills (Python) and experience with EDA tools (HDL simulators, HDL lint).
- Strong teamwork, adaptability, and willingness to work extended hours for mission-critical deadlines.
Education Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (specified). The posting requires 5+ years of relevant RTL/ASIC experience; no alternative "equivalent experience" language was provided.
About the Company
Company: SpaceX
Headquarters: Hawthorne, California, United States
SpaceX is focused on developing space technologies to enable human exploration of Mars and beyond. The company is known for its advancements in rocketry and its Starlink satellite constellation, which delivers high-speed internet globally.
