Senior ASIC Design Engineer – Processor Subsystem

Job Title

Senior ASIC Design Engineer – Processor Subsystem

Role Summary

E-Space is developing LEO satellite IoT systems. This role sits on the processor subsystem team and focuses on configuration, RTL integration, and verification planning for Arm processor IP and associated subsystem components in ASIC designs.

Experience Level

Senior-level role — typically requires 7+ years of ASIC/SoC design experience focused on processor subsystem integration.

Responsibilities

Owner of subsystem integration and verification planning for the processor subsystem; collaborate with SoC architects, verification, and physical design teams.

• Configure and integrate Arm processor IP (e.g., Cortex-M series) and subsystem components: interconnects, memory controllers, peripherals.
• Implement subsystem-level RTL integration ensuring correct connectivity, clocking, and reset domains.
• Translate subsystem requirements from SoC architects into RTL implementation and integration guides.
• Define and develop comprehensive verification testplans covering processor interfaces and IP integration.
• Identify and resolve integration issues across IP boundaries, including protocol and domain crossings.
• Support synthesis and timing closure activities with the physical design team.
• Participate in design reviews and improve integration methodologies.
• Support post-silicon bring-up and debug of the processor subsystem.

Requirements

Looking for hands-on RTL/processor-subsystem engineers who can lead integration and work with verification and physical design teams.

Must-have:

• 7+ years of ASIC/SoC design experience with processor subsystem integration.
• Strong RTL design and integration experience using SystemVerilog or VHDL.
• Experience with AMBA protocols (AHB, APB, AXI) in subsystem contexts.
• Proven collaboration with verification teams on testplan definition and functional coverage.
• Familiarity with EDA tools for RTL compile and simulation (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
• Familiarity with synthesis flows and static timing analysis for processor subsystems.

Nice-to-have:

• Experience with Arm Corstone or similar processor subsystem reference designs and IP configuration tools.
• Knowledge of low-power design techniques and UPF-based power-aware design flows.
• Experience with scripting for design automation (Python, Tcl, Perl).
• Background in satellite IoT, embedded communications, or constrained application domains.
• Experience with post-silicon bring-up and debug of processor subsystems.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field (e.g., EE, CE, Computer Science, or equivalent).

About the Company

Company: E-Space

Headquarters: Saratoga, CA, United States

E-Space develops low Earth orbit (LEO) satellite systems to enable hyper-scaled Internet of Things (IoT) connectivity. The company designs advanced satellite hardware and communication systems to reduce costs, improve scalability, and deliver actionable intelligence from space.