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Senior ASIC Design Engineer - Memory & Cache Controller

Qualcomm
October 13, 2026
Full-time
On-site
San Diego, California, United States
ASIC Design Jobs, Level - Senior

Job Title

Senior ASIC Design Engineer - Memory & Cache Controller

Role Summary

Join Qualcomm's ASIC Engineering team to design and deliver next-generation high-speed memory and cache controller IP for production SoCs. The role covers architecture, RTL implementation, verification support, and integration into chip designs.

Work with cross-functional teams to optimize performance, timing, power, and reliability for memory subsystems used with CPUs, DSPs, and multimedia processors.

Experience Level

Senior-level. The posting cites ~3 years of ASIC design experience as guidance; candidates with more experience are expected to handle architecture, implementation, and chip integration responsibilities. Recent graduates may be considered per the original posting.

Responsibilities

Primary responsibilities include delivery of memory/cache controller IP from architecture through silicon integration.

  • Define, model, and drive architecture and micro-architecture for high-speed memory and cache controllers.
  • Implement and deliver RTL and related documentation for IP blocks.
  • Collaborate with verification engineers to ensure correctness and coverage; support gate-level simulations.
  • Debug designs and support integration into SoCs.
  • Perform synthesis, timing closure, power analysis, and provide physical design support.
  • Improve design methodology to increase productivity and quality.

Requirements

Must-have technical skills and experience; preferred items noted.

  • Proven ASIC RTL design experience, including synthesis and timing closure.
  • Experience with LPDDR memory and cache controller design.
  • Knowledge of on-chip tightly coupled SRAM and L3 cache controller architecture/design.
  • Familiarity with NoC-based architectures and front-end interfacing to CPU, DSP, and multimedia processors.
  • Understanding of memory transaction ordering and enforcement per ISA specifications.
  • Experience with CPU/bus architectures (x86 or ARM) and system integration.
  • Strong debugging skills and experience supporting block integration into chips.
  • Nice-to-have: exposure to HBM memory designs.

Education Requirements

Bachelor's or Master's degree in Science, Engineering, or a related field is stated. The posting also accepts equivalent practical experience.


About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.

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Date Posted: 2026-10-09