Senior ASIC Design Engineer, Low Power Audio AI Subsystems
QualcommJob Title
Senior ASIC Design Engineer, Low Power Audio AI Subsystems
Role Summary
Work on ultra-low power audio and on-device AI subsystems within Qualcomm's ASIC engineering organization. The role focuses on digital micro-architecture, RTL implementation, power optimization, and system integration for audio/AI IP that interfaces with SoCs.
The engineer will collaborate with verification, implementation, and silicon-debug teams to meet functional, power, area, and timing targets for premium mobile, compute, automotive, and IoT products.
Experience Level
Senior. The posting lists minimum professional ASIC hardware design experience of 2+ years; degree-specific experience adjustments are also specified (see Education Requirements).
Responsibilities
Primary responsibilities include design, implementation, analysis, and cross-team integration for low-power audio and AI IP blocks.
- Define micro-architecture and module specifications for digital audio and AI IP and SoC interfaces.
- Implement modules and subsystems in Verilog RTL and integrate third-party or internal IP.
- Analyze trade-offs among performance, area, power, and system cost for design choices.
- Identify and implement power-optimization opportunities for ultra-low power designs; perform power projection and what-if analysis.
- Collaborate with verification teams to debug tests at module, subsystem and SoC levels pre- and post-silicon.
- Work with implementation teams to review synthesis results, power metrics, and achieve static timing closure.
- Support silicon debug and correlate silicon behavior to functional and power objectives.
Requirements
Must-have technical skills and conditions are listed first, followed by preferred/beneficial skills.
- Must-have: 2+ years of professional ASIC hardware design and/or implementation experience.
- Must-have: Proficient in Verilog or VHDL RTL with ability to write synthesizable, readable RTL.
- Must-have: Solid understanding of ASIC/VLSI design concepts and logic synthesis using Synopsys and/or Cadence tools.
- Must-have: Legal ability to work in Canada.
- Preferred: Power analysis, power modeling, and low-power RTL design experience.
- Preferred: Clock-domain crossing techniques and experience with audio IP cores, DSPs, audio interfaces (I2S, PCM, SLIMbus, SoundWire, Audio Codec) and low-power AI/ML accelerators.
- Preferred: Familiarity with tools and flows such as DC, FC, PTPX, Power Compiler, PrimeTime, ModelSim/Modeltech, VCS, and power-theater flows.
- Preferred: Experience with design rule checking (SpyGlass), formal verification (Formality, LEC), post-silicon debug, UVM.
- Preferred: Scripting and programming skills (Python, Perl, TCL, C) and knowledge of bus protocols (APB, AHB, AXI).
Education Requirements
Bachelor's degree in Science, Engineering, or related field plus 2+ years of ASIC design/verification experience; OR Master's degree in Science, Engineering, or related field plus 1+ years of ASIC design/verification experience; OR PhD in Science, Engineering, or related field. (Degrees and associated minimum experience levels are specified in the posting.)
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
