Senior ASIC Design Engineer, Low Power Audio AI Subsystems

Job Title

Senior ASIC Design Engineer, Low Power Audio AI Subsystems

Role Summary

Design and implement ultra-low power digital audio and AI IP blocks for SoC subsystems, focusing on micro-architecture, RTL implementation, power analysis, and integration. Work across design, verification, implementation, and silicon debug teams to meet functional and power targets.

This role supports next-generation low-power audio AI subsystems for mobile, compute, automotive, and IoT products.

Experience Level

Senior. The posting lists a minimum of 2+ years of professional ASIC hardware design or implementation experience (also provides degree-based alternatives: Master's with 1+ year, PhD). The title indicates senior-level responsibility.

Responsibilities

Key responsibilities include designing micro-architecture, implementing RTL, and optimizing for power and performance across the ASIC development cycle.

• Develop micro-architecture and module specifications for digital audio and AI IP blocks and SoC interfaces.
• Implement modules and subsystems and integrate IP from other teams using Verilog RTL.
• Analyze performance, area, power, and system cost tradeoffs for proposed implementations.
• Identify and review opportunities for power optimization in ultra-low power designs.
• Perform power projection and what-if scenario exploration.
• Collaborate with design verification to debug tests at module, subsystem, and SoC levels (pre- and post-silicon).
• Work with implementation (synthesis/place-and-route) teams to review results, power metrics, and reach static timing closure.
• Support silicon debug efforts to correlate functional and power objectives.

Requirements

Must-have technical skills and conditions for the role.

• 2+ years of professional ASIC hardware design and/or implementation experience.
• Proficient in Verilog and/or VHDL; ability to write clean, synthesizable RTL.
• Solid understanding of ASIC/VLSI concepts.
• Experience with logic synthesis using Synopsys and/or Cadence tools.
• Legal authorization to work in Canada.

Preferred / Nice-to-have:

• Experience with power analysis, power modeling, and low-power RTL design.
• Clock domain crossing techniques and low-power design methodology.
• Experience with audio IP cores, DSPs, audio interfaces (I2S, PCM, SLIMbus, SoundWire, Audio Codec) and low-power AI/ML accelerators.
• Familiarity with tools and flows such as DC, FC, PTPX, Power Compiler, Primetime, Modeltech, VCS, and power-theatre flows.
• Experience with design rule checks (Spyglass), formal verification (Formality, LEC), and power simulation.
• Scripting skills (Python, Perl, Tcl or C) and C coding experience.
• Experience with post-silicon debug and UVM.
• Knowledge of bus interface protocols (APB, AHB, AXI).

Education Requirements

One of the following: Bachelor's degree in Science, Engineering, or related field (with 2+ years ASIC design/verification experience); OR Master's degree in Science, Engineering, or related field (with 1+ years ASIC design/verification experience); OR PhD in Science, Engineering, or related field.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.