Senior ASIC Design Engineer, Low Power AI

Job Title

Senior ASIC Design Engineer, Low Power AI

Role Summary

Design and implement Verilog/VHDL RTL for ultra-low power AI and digital audio IP blocks, integrate modules into SoC subsystems, and drive power and performance optimization throughout the ASIC development cycle.

Join the low-power AI/audio ASIC team responsible for micro-architecture, RTL implementation, synthesis reviews, power analysis, and silicon bring-up support.

Experience Level

Senior. The role expects industry ASIC hardware design experience - baseline listed is 2+ years of professional ASIC design/implementation experience (degree-dependent: see Education Requirements).

Responsibilities

Principal responsibilities include micro-architecture, RTL implementation, integration, and power/performance analysis across design, verification, implementation, and silicon debug phases.

• Develop micro-architecture and module specifications for digital audio and AI IP blocks and SoC interfaces.
• Implement modules and subsystems in synthesizable Verilog/VHDL and integrate third-party/internal IP.
• Analyze trade-offs: performance, area, power, and system cost for design alternatives.
• Identify and implement power optimizations for ultra-low power designs; perform power projection and what-if scenario analysis.
• Collaborate with verification to debug module, subsystem, and SoC-level tests (pre- and post-silicon).
• Work with implementation teams to review synthesis results, power metrics, and achieve static timing closure.
• Support silicon debug and correlate silicon results against functional and power objectives.

Requirements

Key must-have skills and technologies followed by preferred skills.

Must-have:

• 2+ years professional ASIC hardware design and/or implementation experience.
• Proficiency in Verilog or VHDL; ability to write clean, synthesizable RTL.
• Understanding of ASIC/VLSI design concepts and flow.
• Experience with logic synthesis using Synopsys and/or Cadence toolflows.
• Legal ability to work in Canada.

Nice-to-have:

• Power analysis, power modeling, and low-power RTL design experience.
• Clock domain crossing techniques and low-power design methodologies.
• Experience with audio IP cores, DSPs, audio interfaces (I2S, PCM, SLIMbus, SoundWire), and low-power AI/ML accelerators.
• Familiarity with implementation and verification tools (DC, FC, PTPX, Power Compiler, PrimeTime, ModelSim/Modeltech, VCS, power-theatre tools).
• Design rule checks and formal verification tools (Spyglass, Formality, LEC) and power simulation tools.
• Scripting skills (Python, Perl, TCL or C) and C coding experience.
• Knowledge of bus protocols (APB, AHB, AXI), UVM, and post-silicon debug.

Education Requirements

Bachelor's degree in Science, Engineering, or related field plus 2+ years ASIC design/verification experience; OR Master's degree in Science, Engineering, or related field plus 1+ years ASIC design/verification experience; OR PhD in Science, Engineering, or related field.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.