Senior ASIC Design Engineer, Low Power AI

Job Title

Senior ASIC Design Engineer, Low Power AI

Role Summary

Design and implement digital IP and sub-systems for ultra‑low power audio and on‑device AI within an ASIC team. Work covers micro-architecture, RTL implementation, power analysis/optimization, synthesis, timing closure, and silicon bring-up.

Experience Level

Senior - the role expects experienced engineers (posting lists 2+ years industry ASIC hardware design experience as a minimum).

Responsibilities

Primary engineering responsibilities throughout the ASIC development cycle:

• Develop micro-architecture and module specifications for digital audio and AI IP blocks and SoC interfaces.
• Implement modules and sub-systems in Verilog RTL and integrate IP from other teams.
• Analyze performance, area, power, and cost trade-offs; identify power-optimization opportunities for ultra-low power designs.
• Perform power projection and what-if scenario analysis.
• Collaborate with verification teams to debug module, subsystem, and SoC level tests pre- and post-silicon.
• Work with implementation teams to review synthesis results, power metrics, and achieve static timing closure.
• Support silicon debug and correlate silicon results to functional and power objectives.

Requirements

Key must-have skills and qualifications. Preferred skills are listed separately.

• Must-have: 2+ years professional ASIC hardware design or implementation experience.
• Must-have: Proficient in Verilog or VHDL; able to write synthesizable, readable RTL.
• Must-have: Understanding of ASIC/VLSI concepts and experience with logic synthesis (Synopsys and/or Cadence flow).
• Must-have: Legal ability to work in Canada.
• Nice-to-have: Power analysis/modeling and low-power RTL design experience.
• Nice-to-have: Clock domain crossing techniques and power/performance experience with audio IP, DSPs, audio interfaces, or low-power AI accelerators.
• Nice-to-have: Familiarity with DC, Fusion Compiler, PrimeTime, power compiler, ModelSim/Modeltech/VCS, power theatre tools, or similar.
• Nice-to-have: Design rule check tools (e.g., Spyglass), formal verification (Formality, LEC), post-silicon debug, UVM.
• Nice-to-have: Scripting or coding skills (Python, Perl, TCL, C) and knowledge of bus protocols (APB, AHB, AXI).

Education Requirements

Bachelor's degree in Science, Engineering, or related field plus 2+ years ASIC design/verification experience; OR Master’s degree in Science, Engineering, or related field plus 1+ year experience; OR PhD in Science, Engineering, or related field. Equivalent practical experience is acknowledged by the listed experience-based minimums.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.