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Senior ASIC Design Engineer

Palo Alto Networks
October 7, 2026
Full-time
On-site
Santa Clara, California, United States
$156,400 - $253,000 USD yearly
RTL Design Jobs, Level - Senior

Job Title

Senior ASIC Design Engineer

Role Summary

Design and deliver front-end digital logic for next-generation firewall ASICs, owning modules from specification through silicon bring-up. Work on an on-site ASIC engineering team alongside verification and physical-design engineers to meet aggressive performance, power, area, and schedule targets.

Experience Level

Senior - requires significant experience (10+ years) in front-end ASIC design and shipping production silicon.

Responsibilities

Main responsibilities include:

  • Write clear design and micro-architecture specifications.
  • Implement SystemVerilog RTL that meets area, performance, and power targets.
  • Verify blocks using simulation, emulation, formal methods, and silicon bring-up.
  • Collaborate with verification engineers to debug complex scenarios, close coverage, and add design-for-debug features.
  • Partner with physical-design teams: review synthesis/timing reports, rewrite RTL to close critical paths, and consult on floor-planning for congestion/routability.
  • Lead module integration: select, configure, and integrate complex IP for high-speed interfaces.
  • Explore and pilot AI-driven design or verification flows to reduce schedule risk.

Requirements

Must-have qualifications and skills:

  • 10+ years front-end ASIC design ownership; experience shipping 2+ chips to mass production.
  • Expert SystemVerilog RTL skills.
  • Proven experience selecting, integrating, and configuring complex IP for high-speed interfaces (PCIe, Ethernet, DDR, etc.).
  • Scripting proficiency (Python, C/C++, Perl, bash or tcsh).
  • Strong micro-architecture and datapath design experience for synchronous/asynchronous digital logic.
  • Demonstrated debugging across simulation, emulation, and silicon; able to analyze timing, power, and area reports and drive fixes.
  • Excellent leadership, collaboration, and written/verbal communication skills.

Nice-to-have:

  • Networking or cybersecurity domain knowledge.
  • Experience with search-algorithm accelerators.
  • Formal-verification ownership.
  • Hands-on silicon validation and lab bring-up experience.

Education Requirements

BS in Electrical Engineering (EE), Computer Engineering (CE), or Computer Science (CS) required. MSEE or equivalent military experience preferred.


About the Company

Company: Palo Alto Networks

Headquarters: Santa Clara, California, United States

Global cybersecurity company that develops network and cloud security products, including next-generation firewalls, endpoint protection, threat intelligence, and AI-driven security platforms for enterprises and service providers.

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Date Posted: 2026-10-07