Senior ASIC Design Engineer - DSP/Analog/SerDes

Job Title

Senior ASIC Design Engineer - DSP/Analog/SerDes

Role Summary

Design and deliver high-performance ASIC blocks and subsystems for optical communication systems, focusing on digital RTL, DSP integration, SerDes interfaces, and mixed-signal interaction. Work within a cross-functional engineering team through architecture, RTL, implementation, tapeout, and silicon validation.

This is a hands-on engineering role at a semiconductor startup; you will collaborate with Analog, SerDes, Verification, Physical Design, and Systems teams to meet performance, power, and area targets.

Experience Level

Senior - 10+ years of experience in digital ASIC design, including ownership of complex ASIC blocks or subsystems.

Responsibilities

Technical responsibilities and contributions expected from day one.

• Design and implement digital circuits and ASIC blocks using Verilog/SystemVerilog.
• Develop and integrate DSP, digital communications, and high-speed SerDes functionality into ASICs.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams for mixed-signal integration.
• Perform synthesis, static timing analysis, lint, formal equivalence, and Clock Domain Crossing (CDC) analysis; support signoff activities.
• Optimize designs for performance, power, and area (PPA).
• Run RTL simulation, debug functional issues, and support block- and top-level integration and verification.
• Support silicon bring-up, lab validation, and system-level troubleshooting.
• Participate in architecture and design reviews and mentor other engineers.
• Develop scripts and automation (Python, Tcl, or similar) to improve design and verification efficiency.

Requirements

Must-have technical skills and experience are listed first; preferred items follow.

• Extensive experience with Verilog and/or SystemVerilog and RTL design practices.
• Deep knowledge of digital design principles and ASIC development methodologies.
• Hands-on experience with ASIC design flows and industry-standard EDA tools.
• Experience with synthesis, static timing analysis, linting, CDC analysis, formal verification, and RTL simulation.
• Familiarity with verification methodologies (e.g., UVM) and formal techniques.
• Proven ability to optimize for PPA and meet aggressive performance targets.
• Strong analytical, problem-solving, communication, and teamwork skills appropriate for a fast-paced startup.
• Ability to work onsite in Ottawa and participate in silicon bring-up and lab validation.

Nice-to-have:

• Experience with optical communications, coherent DSP, FEC, modulation/equalization, or high-speed networking.
• Detailed SerDes experience (TX/RX datapaths, CDR/PLL, CTLE, DFE, ADC/DAC interfaces).
• Experience with MATLAB, Python, Tcl for modeling and automation.
• Experience taking ASICs from architecture/RTL through synthesis, PnR, tapeout, and silicon bring-up.
• Experience with advanced semiconductor process technologies and mixed-signal interaction.

Education Requirements

Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field (as stated in the posting).

About the Company

Company: Celero Communications

Headquarters: Ottawa, Ontario, Canada

Designs and develops optical transceivers and ASIC solutions for next-generation optical modems, focusing on digital ASIC/RTL design, verification, and optical communication technologies.