Senior ASIC Design Engineer – DSP/Analog/SerDes

Job Title

Senior ASIC Design Engineer – DSP/Analog/SerDes

Role Summary

Design and develop high-performance ASIC blocks for high-speed optical communication systems. Work on digital RTL, DSP integration, SerDes interfaces and mixed-signal collaboration across architecture, verification, physical design, and systems teams.

Responsible for end-to-end implementation, optimization for performance/power/area, and silicon bring-up of complex ASIC subsystems.

Experience Level

Senior - typically 10+ years of digital ASIC design experience with ownership of complex ASIC blocks or subsystems.

Responsibilities

Key responsibilities include design, integration, verification, and automation for mixed-signal ASIC projects.

• Design and implement digital ASIC blocks using Verilog and SystemVerilog.
• Develop and integrate DSP, digital communication, and high-speed SerDes functionality.
• Perform synthesis, static timing analysis (STA), lint, formal equivalence, and Clock Domain Crossing (CDC) verification.
• Optimize designs for performance, power, and area (PPA).
• Run RTL simulation, debug, and support block-level and top-level integration and silicon bring-up.
• Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams.
• Participate in architecture and design reviews and provide technical guidance to other engineers.
• Develop scripts and automation using Python, Tcl, or similar languages to improve design and verification efficiency.

Requirements

Must-have technical skills and experience.

• 10+ years of digital ASIC design experience with ownership of complex ASIC blocks or subsystems.
• Strong proficiency in Verilog and/or SystemVerilog and solid RTL design skills.
• Hands-on experience with ASIC design flows and industry-standard EDA tools; synthesis and STA experience.
• Practical knowledge of DSP, high-speed SerDes, digital communications, and optical communications.
• Experience with formal verification, lint, CDC verification, and RTL simulation.
• Ability to work cross-functionally on mixed-signal ASIC projects and support silicon bring-up.
• Experience scripting or automating flows with Python, Tcl, or similar.
• Nice-to-have: familiarity with UVM and advanced verification methodologies; experience with FEC, equalization, or modulation techniques.

Education Requirements

Master's or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.

About the Company

Company: Celero Communications

Headquarters: Ottawa, Ontario, Canada

Designs and develops optical transceivers and ASIC solutions for next-generation optical modems, focusing on digital ASIC/RTL design, verification, and optical communication technologies.