Senior ASIC Design Efficiency Engineer
Design methodology engineer focused on improving performance, power and area (PPA) for NVIDIA GPUs and hardware accelerators across mobile, embedded and datacenter platforms.
Work with architects, RTL designers, verification and VLSI teams to develop methodology, infrastructure, and verified RTL that meet aggressive PPA targets.
Senior β 12+ years of relevant industry experience.
The role combines RTL implementation, methodology development, and cross-discipline collaboration to deliver efficient silicon.
Must-have skills and experience.
Nice-to-have:
Bachelor's degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.
Company: NVIDIA
Headquarters: Santa Clara, California, USA
NVIDIA is a global leader in accelerated computing, renowned for its innovative solutions in AI and digital twins that transform diverse industries. The company specializes in networking technologies, providing end-to-end InfiniBand and Ethernet solutions for servers and storage that optimize performance and scalability. NVIDIA serves sectors such as high-performance computing, enterprise data centers, and cloud computing, constantly reinventing its products and services to stay ahead in the market.
