Senior Application Engineer
SynopsysJob Title
Senior Application Engineer
Role Summary
Customer-facing engineering role supporting Synopsys PVT Monitor IP customers worldwide. Acts as the primary technical interface between semiconductor customers and the PVT IP R&D organization to enable RTL-to-silicon integration, silicon bring-up, validation, and production sign-off.
Work with sales, IP development, validation, and documentation teams to support releases, interoperability, and customer enablement for mixed-signal and digital IPs.
Experience Level
Senior-level. The posting indicates 3+ years of relevant SoC or semiconductor IP experience in integration, verification, physical design, timing, or DFT.
Responsibilities
Primary technical responsibilities and customer support tasks:
- Enable customers for RTL-to-silicon integration of hard macros and PVTC controllers.
- Advise on floorplanning, placement, routing, shielding, IR drop, and signal integrity for IP integration.
- Support timing closure and sign-off across IP boundaries (STA, Liberty/SDF, variation modelling).
- Provide DFT and production test support, including scan, ATPG, ATE strategies, and silicon validation.
- Assist with verification, bring-up, debug, low-power validation, and firmware integration.
- Translate calibration and accuracy requirements into firmware and test solutions.
- Troubleshoot customer issues, perform root-cause analysis, reproduce failures, and coordinate resolution with R&D.
- Partner with sales and internal teams to support new releases and customer technical engagement.
Requirements
Key technical skills and experience expected for successful candidates.
- 3+ years experience in SoC or semiconductor IP across areas such as IP/SoC integration, RTL (Verilog/SystemVerilog), design verification, place-and-route, timing/Liberty, or DFT/ATPG.
- Ability to debug simulation mismatches (X/Z, handshake stalls, model vs. netlist) and distinguish testbench/model issues from RTL defects.
- Working knowledge of STA using .lib/.db/SDF, including constraint arcs (setup/hold).
- Working knowledge of scan architecture and ATPG deliverables versus functional simulation.
- Strong written English for customer-facing technical communication.
- Familiarity with Synopsys toolset such as VCS, Verdi, Fusion Compiler, PrimeTime, and SpyGlass/VC Static.
- Customer-facing AE/FAE or design-services experience and experience with mixed-signal-aware digital integration (ESD, analog test pins, supply sequencing).
- Experience with advanced-node (FinFET) SoC and IP delivery.
Education Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is stated. A Master's degree in a related field is also listed.
About the Company
Company: Synopsys
Headquarters: Mountain View, California, USA
Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.
