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Senior Analog/Mixed-Signal IC Design Engineer - Acacia (Hybrid)

Cisco Systems
June 02, 2026
Full-time
Remote friendly (San Jose, California, United States)
Worldwide
$191,400 - $281,400 USD yearly
ASIC Design Jobs, Level - Senior

Job Title

Senior Analog/Mixed-Signal IC Design Engineer - Acacia (Hybrid)

Role Summary

Join the Mixed-Signal IC design group developing high-speed (≥25 Gb/s) and high-accuracy analog designs for Acacia photonic transceivers used in 100G–1T fiber‑optic systems. The role architects, implements, and productizes ultra-deep-submicron CMOS analog/mixed-signal blocks and coordinates with DSP, system, package and module teams.

This is a hybrid role requiring three days per week in the San Jose, CA office.

Experience Level

Senior — senior-level IC design engineer. Hiring guidance in the posting equates to approximately 5+ years with a PhD, 8+ years with an MS, or 12+ years with a BSEE, or equivalent practical experience.

Responsibilities

Key responsibilities include design ownership, technical leadership, and cross-team collaboration from concept through production.

  • Architect, design, layout, characterize, and productize ultra-deep-submicron CMOS analog/mixed-signal ICs.
  • Lead large complex chip blocks, mentor engineers, and track deliverables and schedules.
  • Participate in peer reviews and establish robust design methodology from concept to production.
  • Collaborate with packaging and hardware teams to meet signal and power integrity specifications.
  • Develop high-speed AMS circuits and associated test and measurement plans for production readiness.

Requirements

Must-have skills and experience for immediate contribution.

Must-have
  • Design, simulation, and measurement of high-speed ICs in at least three areas such as serializers/deserializers, data converters, voltage regulators, output drivers, PLLs/clock distribution, opamps, programmable gain amplifiers, or equalization.
  • Practical mixed-signal simulation experience (Spectre/APS/SpectreX) and familiarity with Cadence Virtuoso flows.
  • Experience with AMS verification, lab characterization, and mixed-signal test methodologies.
  • Ability to produce layouts compatible with manufacturing and to work with cross-functional teams on integration.

Nice-to-have

  • Experience with FinFET technologies and high-frequency layout for passive components (inductors, transformers, transmission lines).
  • Floorplanning experience for power/ground and analog/digital signal routing.
  • Custom transistor layout and design-for-manufacturability experience.
  • ESD laboratory practices and methodology.
  • Familiarity with Matlab and EM extraction/simulation tools (e.g., EMX).

Education Requirements

Posting specifies degree-based hiring guidance: BSEE with 12+ years of experience, MS with 8+ years, or PhD with 5+ years — or equivalent practical experience. Fields implied include Electrical Engineering or related technical disciplines. No specific certifications were listed.


About the Company

Company: Cisco Systems

Headquarters: San Jose, CA, United States

Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).

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Date Posted: 2026-06-03