Senior Analog/mixed-signal IC Design Engineer - Acacia
Cisco SystemsJob Title
Senior Analog/mixed-signal IC Design Engineer - Acacia
Role Summary
Member of the mixed-signal IC design group responsible for architecting, designing, laying out, measuring and productizing ultra-deep-submicron CMOS analog and mixed-signal circuits for high-speed optical transceivers (100G–1T).
The team interfaces with digital/DSP, system, package and module design groups to integrate analog blocks into complex ASICs and ensure signal and power integrity.
Experience Level
Senior-level role. Typical candidates have multiple years of hands-on mixed-signal IC design and verification experience (senior competence expected).
Responsibilities
Deliver and own complex mixed-signal IC blocks from architecture through production; collaborate across disciplines to meet system requirements.
- Architect, design, layout, simulate, measure and productize ultra-deep-submicron CMOS mixed-signal circuits.
- Lead design efforts for large blocks on complex chips; track deliverables and participate in design reviews.
- Mentor and guide junior engineers; establish and apply robust design methodology.
- Collaborate with packaging and hardware teams to meet signal and power integrity specifications.
- Develop high-speed analog/mixed-signal circuits for optical transceivers and validate them in lab measurements.
- Drive design-for-manufacturability and ESD-aware design practices into production flows.
Requirements
Must-have technical skills and experience to perform the role effectively.
- Proven track record designing, simulating and measuring high-speed ICs; experience covering multiple functional areas is required.
- Hands-on experience with high-speed serial link building blocks (serializers/deserializers, data converters) and analog front-end components (output drivers, op amps, programmable gain amplifiers, equalization).
- Experience with PLLs, clock transmission/propagation and power-regulation circuitry in high-speed systems.
- Strong mixed-signal layout skills and ability to floorplan power/ground and analog/digital signal routing for complex chips.
- Experience delivering production-ready ASIC blocks and collaborating with cross-functional teams (digital, package, system).
- Leadership: able to lead a large block, drive peer reviews, and mentor team members.
- Nice-to-have: FinFET process experience, passive HF component design (inductors, transformers, transmission lines), custom transistor layout, ESD lab methodology, and tools such as Cadence Virtuoso, Spectre/APS/SpectreX, Matlab, EMX and AMS simulation flows.
Education Requirements
Degree and experience combinations accepted: BSEE with 12+ years of relevant experience, MS in a relevant field with 8+ years, or PhD with 5+ years; equivalent practical experience is also acceptable. Typical fields: Electrical Engineering, Computer Engineering, or related technical disciplines.
About the Company
Company: Cisco Systems
Headquarters: San Jose, CA, United States
Cisco Systems is a global technology company that designs and sells networking hardware, telecommunications equipment, software, and services. It provides enterprise and service-provider networking, security, collaboration, and optical communications solutions (including Acacia Communications technologies for high-speed optical interconnects).
