Senior Analog IP Integration, Power, and SI Engineer

Job Title

Senior Analog IP Integration, Power, and SI Engineer

Role Summary

Join Intel's Hard IP and Test Chip Development team within Central Engineering to design and integrate analog and mixed-signal IP for high-speed IO and die-to-die systems. The role focuses on IP floor planning, power delivery, bump maps, and signal integrity across advanced process nodes.

This position works with cross-functional global teams (architecture, logic, layout, verification, manufacturing) and participates from specification through post-silicon validation. The role expects in-office presence at least four days per week.

Experience Level

Senior — requires 5+ years of professional experience in analog/mixed-signal circuit design, especially for high-speed SerDes or similar applications.

Responsibilities

Primary responsibilities include design, verification, and cross-team integration of analog IP and subsystems.

• Design and simulate analog/mixed-signal circuits (amplifiers, data converters, voltage regulators, PLLs, RX/TX blocks).
• Develop transistor-level circuit architectures and optimize layouts with layout engineers.
• Define IP top-level floor plans, bump maps, and power delivery schemes.
• Perform signal integrity and system-level performance analysis; optimize for power, area, and performance.
• Lead projects from specification to silicon validation; drive design reviews and methodology adherence.
• Develop test plans and oversee post-silicon characterization and debug.
• Mentor junior engineers and collaborate with global teams to ensure design interoperability across process nodes.

Requirements

Must-have technical skills and experience; preferred items noted separately.

• 5+ years experience in analog/mixed-signal circuit design for high-speed SerDes or similar systems.
• Hands-on experience with PLL, CDR, CTLE, DFE, ADC, RX AFE, transmitter design, or power delivery and IP top-level performance work.
• Experience with high-speed IO calibration/training algorithms and signal integrity analysis.
• Proven use of analog design and simulation tools (Cadence Virtuoso/ADE, HSPICE, or equivalent).
• Experience with advanced FinFET CMOS process technologies and post-silicon lab validation/debug.
• Strong communication, documentation, and cross-functional collaboration skills.
• Nice-to-have: Verilog-A modeling, MATLAB, automation scripting (Python, Tcl), exposure to PCIe Gen5/6/7 or next-gen standards, and package/channel modeling experience.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field (stated with 5+ years of experience). Preferred: Master's degree in Electrical/Electronics Engineering or related discipline (listed as preferred with ~4+ years). Fields mentioned include electrical/electronics engineering and related technical disciplines. Certifications not specified. "Related field" language is allowed.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.