Senior Analog IC Layout Engineer - MCU

Job Title

Senior Analog IC Layout Engineer - MCU

Role Summary

The Senior Layout Engineer is responsible for the physical implementation of complex analog, mixed-signal, and custom IC designs from floorplanning through tape-out. The role focuses on meeting performance, quality, reliability, area, and schedule targets while collaborating with design, verification, technology, and product teams.

The engineer provides technical leadership, mentors junior staff, drives methodology improvements, and helps mitigate project risks to ensure successful silicon delivery.

Experience Level

Senior - approximately 8–12+ years of custom analog/mixed-signal layout experience in deep sub-micron CMOS.

Responsibilities

Deliver and lead layout tasks for analog and mixed-signal ASIC blocks, ensuring manufacturability and specification compliance.

• Lead layout implementation for complex analog, mixed-signal, and custom digital blocks.
• Drive floorplanning, device matching, routing strategies, and layout optimization for performance, area, power, and reliability.
• Perform and review physical verification: DRC, LVS, ERC, EM/IR, latch-up, density, and reliability checks.
• Collaborate with design, verification, technology, and product teams to resolve layout issues and meet milestones.
• Support advanced-node technologies including FinFET processes; contribute to methodology improvements and best practices.
• Provide technical guidance and mentorship to junior engineers and contractors.
• Assess project risks, estimate layout effort, and drive execution to meet aggressive schedules.

Requirements

Must-have skills and experience for successful performance in this role.

• 8–12+ years' practical experience in custom analog/mixed-signal layout in deep sub-micron CMOS.
• Expertise with Cadence Virtuoso XL, floorplanning, constraint-driven layout methodologies, and physical verification flows (PVS DRC/LVS/ERC).
• Strong knowledge of matching techniques (common centroid), shielding, noise isolation, ESD-aware layout, power distribution, and DFM practices.
• Experience with EM/IR analysis, parasitics, high-speed routing, and multiple voltage domains.
• Proven experience with analog-on-top and digital-on-top chip layouts and successful tape-outs.
• Familiarity with PLLs, oscillators, ADC/DAC, LDOs, bandgaps, and high-speed interface circuits.
• Ability to make independent technical trade-offs, solve complex implementation issues, and drive execution under schedule pressure.
• Strong communication, stakeholder management, and cross-functional leadership skills; ability to mentor others.
• Fluent in English.
• Nice-to-have: SKILL or Perl scripting.

Education Requirements

Bachelor of Science in Electrical Engineering (BSEE) or Master of Science in Electrical Engineering (MSEE) as stated in the posting.

About the Company

Company: NXP Semiconductors

Headquarters: Nijmegen, Netherlands

NXP Semiconductors N.V. is a global semiconductor company that provides High Performance Mixed Signal and Standard Product solutions. With over 45,000 employees and operations in more than 35 countries, NXP is a leader in secure connectivity solutions for embedded applications, catering to automotive, industrial IoT, mobile, and communication infrastructure markets. The company is committed to innovation and sustainability, advancing a smarter, safer, and more sustainable world through technology.