Senior Analog Engineering Manager
RenesasJob Title
Senior Analog Engineering Manager
Role Summary
Lead the architecture, design, delivery, and post-silicon bring-up of DDR5 PHYs and contribute to DDR6-ready architectures. Manage a team of analog and mixed-signal designers and own cross-functional execution with digital, SoC, packaging, SI/PI, validation, and product teams.
The role combines hands-on technical leadership on high-speed memory interfaces with people management, program ownership, and roadmap planning.
Experience Level
Senior-level. Requires 12+ years of analog/mixed-signal IC design experience with a deep focus on high-speed memory interfaces and at least 5+ years of people-management and technical leadership.
Responsibilities
Accountable for technical delivery, team leadership, and cross-functional coordination for DDR5 and DDR6 PHY projects.
- Own architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures.
- Provide technical oversight of high-speed TX/RX datapaths, advanced equalization, termination and training circuits, DLL/PLL-based clocking, voltage/reference generation and power-aware IO.
- Drive closure on timing, jitter, noise, signal/power integrity, and PVT robustness for multi-GHz operation.
- Ensure compliance with JEDEC DDR5 specifications and alignment with DDR6 industry direction.
- Lead post-silicon bring-up, characterization, debug, and yield improvement, including lab and customer-system correlation.
- Build, mentor, and scale an analog/mixed-signal design team; set technical direction and performance expectations.
- Balance schedule, quality, and risk across programs and manage multiple concurrent tape-outs where required.
- Partner with digital PHY/controller teams, SoC integration, package/PCB/SI/PI, validation, product, program management, customers, foundries, IP vendors, and standards bodies.
- Establish and improve design signoff methodologies, mixed-signal verification, simulation accuracy, and silicon debug efficiency; drive roadmap planning.
Requirements
Must-have technical and leadership skills for immediate contribution and delivery.
- 12+ years of analog/mixed-signal IC design experience focused on high-speed memory interfaces.
- 5+ years of people-management and technical leadership experience.
- Hands-on delivery experience with DDR5 PHYs or late-stage DDR4 designs transitioning to DDR5.
- Deep expertise in high-speed IO design, signal integrity, PLL/DLL and low-jitter clocking architectures.
- Experience with advanced equalization, termination, training circuits, and power-aware IO design.
- Proven capability in mixed-signal verification, silicon validation, post-silicon debug, and lab/customer correlation.
- Strong knowledge of timing, jitter, noise, SI/PI, and PVT robustness at multi-GHz data rates.
- Experience interfacing with foundries, IP vendors, and standards organizations; able to drive external technical partnerships.
Nice-to-have:
- Direct involvement in DDR6 architectural studies or early-stage development.
- Experience at advanced process nodes (7nm, 5nm, or below) and multi-generation PHY platforms.
- Proven track record leading teams delivering multiple concurrent tape-outs and communicating with executive stakeholders.
Education Requirements
Bachelor's or Master's degree in Electrical Engineering required; PhD preferred.
About the Company
Company: Renesas
Headquarters: Hitachinaka, Japan
Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.
