Senior Analog Design Engineer

Job Title

Senior Analog Design Engineer

Role Summary

Senior engineer on the Hard IP and Test Chip Development team responsible for architecting, designing, and validating analog and mixed-signal IP for high-speed IO and die-to-die interfaces across advanced process nodes. The role leads projects from specification through silicon validation and works closely with layout, verification, system architects, manufacturing and global development teams.

This position operates on a hybrid schedule with an expectation to work in the office at least 4 days per week; team locations include Phoenix, AZ, Fort Collins, CO and Hillsboro, OR.

Experience Level

Senior — typically 6+ years of experience in analog/mixed-signal circuit design for high-speed SerDes or similar applications.

Responsibilities

Lead the design, verification, and delivery of high-performance analog IP and subsystems.

• Design and simulate analog/mixed-signal circuits (amplifiers, data converters, voltage regulators, PLLs, CDRs, RX/TX blocks).
• Develop circuit architectures and execute detailed transistor-level design.
• Create and optimize layouts in collaboration with layout engineers and ensure top-level IP floor planning, power delivery, and bump mapping.
• Perform circuit analysis, simulation, and verification using industry-standard tools and automation techniques.
• Lead projects from specification to silicon validation; drive design reviews and enforce design methodology.
• Mentor junior engineers and provide technical leadership across multi-site teams.
• Develop test plans, oversee silicon characterization, and perform pre- and post-silicon debug and validation.
• Optimize designs for performance, power, and area while ensuring compliance with specifications and standards.
• Collaborate with cross-functional teams including architecture, logic, verification, physical design, manufacturing, and SOC partners to ensure interoperability.

Requirements

Must-have:

• 6+ years of analog/mixed-signal design experience for high-speed SerDes or equivalent applications.
• Proven experience with one or more: PLL, CDR, CTLE, DFE, ADC, RX AFE, TX, power delivery, IP floor planning, or IP top-level performance simulation.
• Experience with high-speed IO calibration and training algorithms.
• Familiarity with high-speed communication standards (examples: UCIE, PCIe Gen5/Gen6/Gen7).
• Strong grasp of analog fundamentals: noise, linearity, matching, and stability.
• Hands-on experience with advanced FinFET CMOS process technologies.
• Proficiency with analog design and simulation tools (Cadence Virtuoso/ADE, HSPICE or equivalent).
• Experience with post-silicon validation, lab measurements, and debug of analog circuits.
• Effective communication, documentation, and ability to work across global, cross-functional teams.

Nice-to-have:

• Experience with Verilog-A modeling, MATLAB simulations, and automation scripting (Python, Tcl).
• Exposure to next-generation standards (PCIe 6.0, 800G Ethernet, JESD) and advanced package technologies.
• Strong signal integrity understanding, channel modeling, and system-level link analysis experience.

Education Requirements

Bachelor's degree in Electrical Engineering, Electronics Engineering, or a closely related technical field is required. A Master's degree in Electrical/Electronics Engineering or related discipline is preferred. No specific certifications were listed.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.