Senior Analog Design Engineer

Job Title

Senior Analog Design Engineer

Role Summary

Join the Hard IP and Test Chip Development team within Intel's Central Engineering Group to design, develop, and optimize analog and mixed-signal integrated circuits for high-speed IO and die-to-die interfaces across advanced process nodes.

The role leads analog block and IP-level design from specification through silicon validation, collaborating with architecture, logic, layout, verification, and post-silicon teams across multiple sites.

Experience Level

Senior-level. The posting specifies 6+ years of relevant analog/mixed-signal design experience; senior responsibilities include technical leadership and mentoring.

Responsibilities

Deliver analog/mixed-signal IP and lead design projects through implementation and silicon validation.

• Design, simulate, and optimize analog/mixed-signal circuits (amplifiers, converters, regulators, PLLs, SerDes blocks).
• Define circuit architectures and perform transistor-level design and layout co-optimization with layout engineers.
• Lead projects from specification to silicon, run design reviews, and enforce design methodologies.
• Collaborate with cross-functional global teams (architecture, logic, physical design, layout, manufacturing, validation).
• Develop test plans, oversee silicon characterization, and debug pre- and post-silicon issues.
• Optimize designs for performance, power, area, signal integrity, and manufacturability.
• Mentor junior engineers and provide technical guidance.

Requirements

Must-have technical skills and practical experience for immediate contribution.

• 6+ years experience in analog/mixed-signal design for high-speed SerDes or similar applications.
• Proven experience with one or more: PLL, CDR, CTLE, DFE, ADC, RX AFE, TX, power delivery, IP floor planning, top-level IP performance simulation, signal integrity analysis.
• Experience with high-speed IO calibration and training algorithms and standards such as UCIE and PCIe (Gen5/Gen6/Gen7).
• Hands-on experience with advanced FinFET CMOS process technologies.
• Proficiency with analog design and simulation tools (Cadence Virtuoso/ADE, HSPICE, or equivalent) and familiarity with approaches enabling automation and AI-supported flows.
• Post-silicon validation experience: lab measurements, debug, and silicon characterization.

Nice-to-have:

• Exposure to next-generation standards (PCIe 6.0, 800G Ethernet, JESD) and advanced package technologies.
• Experience with Verilog-A modeling, MATLAB simulation, and automation scripting (Python, Tcl).
• Strong background in signal integrity, channel modeling, and system-level link analysis.
• 7+ years experience in analog design for high-speed SerDes and/or die-to-die applications.

Education Requirements

Minimum: Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field. Preferred: Master's degree in Electrical/Electronics Engineering or related discipline. (Degrees and related fields are explicitly specified in the posting.)

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.