Senior Analog Design Architect

Job Title

Senior Analog Design Architect

Role Summary

Principal-level analog design leader responsible for macro-level architecture, design, verification, and silicon correlation of SerDes analog IP. The role partners with digital, firmware, and layout teams to deliver silicon-proven TX/RX/clock macros and drives reuse and methodology improvements across product variants and process nodes.

Experience Level

Senior-level individual contributor / technical leader. Role expects extensive experience in SerDes or high-speed analog design (typically 10+ years of relevant experience).

Responsibilities

Deliver architecture, oversee implementation, and ensure quality and silicon readiness for SerDes analog macros.

• Own macro-level architecture, circuit design strategy, and implementation across TX, RX, and clock paths.
• Translate SerDes standards and system requirements into detailed analog specifications and budgets (jitter, noise, linearity, latency, power, area).
• Define scalable, reusable circuit platforms and lead architecture trade-offs across product variants and process nodes.
• Coordinate technical execution among sub-block owners, manage risks, remove blockers, and track schedule alignment.
• Specify interfaces between analog macros and digital calibration/control; collaborate with RTL and firmware teams on algorithms and observability hooks.
• Establish and enforce verification strategies using SPICE, corner and Monte Carlo analysis, aging, mismatch, noise, transient jitter, and PVT sweeps.
• Drive behavioral modeling (Verilog-A) for system validation and improve block-to-top correlation.
• Define silicon correlation plans, map measurements to simulations, and feed improvements back into design.
• Provide layout oversight to minimize parasitics, coupling, mismatch; ensure reliability and ESD are addressed early.
• Mentor junior and mid-level engineers and contribute reusable collateral and methodology improvements.

Requirements

Key technical skills and proven experience required to perform the role.

• Proven track record delivering macro-level SerDes analog IP through tapeout and silicon validation with multiple silicon successes.
• Deep transistor-level design expertise and strong CMOS and FinFET fundamentals.
• Practical experience implementing circuits for TX, RX, and clock paths in SerDes architectures.
• In-depth knowledge of SerDes sub-circuits (equalizers, samplers, drivers, serializers/deserializers, VCOs, phase interpolators, DLLs, PLLs, bandgaps, ADCs/DACs).
• Advanced FinFET layout guidance skills to minimize parasitics and device mismatch; awareness of routing, shielding, EM/IR concerns.
• Understanding of ESD and reliability issues and mitigation techniques in circuit and layout.
• Proficiency with EDA tools for schematic entry, layout, and verification; extensive SPICE simulator use for circuit analysis.
• Familiarity with analog behavioral modeling using Verilog-A.
• Programming experience for automation and analysis: TCL, Perl, C, Python, and MATLAB.
• Demonstrated technical leadership and the potential to lead a team as the organization grows.

Education Requirements

Posting specifies: PhD with 10+ years, or MSc with 12+ years of SerDes or high-speed analog design experience with multiple silicon successes. Fields referenced include SerDes and high-speed analog design. No other degrees, certifications, or "equivalent experience" language is provided.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.