Semiconductor Test Engineer

Job Title

Semiconductor Test Engineer

Role Summary

Lead development and deployment of manufacturing test solutions for next-generation AI accelerator devices across the full silicon lifecycle, from first-silicon bring-up to high-volume production. Partner with design, DFT, packaging, OSATs, and manufacturing teams to define test strategy, develop ATE content, debug silicon issues, and optimize yield, coverage, and test cost.

Experience Level

Mid-level — typically requires 5+ years of hands-on semiconductor test engineering experience.

Responsibilities

Key responsibilities include:

• Develop and maintain ATE test programs for AI accelerator chips targeting high-volume manufacturing.
• Implement manufacturing test content for advanced CMOS designs: high-speed logic, SRAM/DRAM, and high-speed IO blocks.
• Develop and debug structural and functional tests (scan/ATPG, LBIST, MBIST, JTAG, HSIO).
• Bring up first silicon on ATE: pattern debug, tester correlation, shmooing, and corner analysis.
• Test and margin high-speed interfaces such as PCIe Gen5/Gen6 and multi-GHz LPDDR at-speed.
• Execute silicon characterization and failure analysis to identify yield limiters and defect mechanisms.
• Optimize test coverage, test time, and cost while maintaining manufacturing robustness.
• Collaborate with DFT and design teams, OSATs, and external partners on test program execution and debug.
• Support advanced packaging test flows, including die-to-die interconnect testing and package-level thermal considerations.
• Document test programs, debug procedures, and manufacturing release materials; support qualification, reliability testing, and production ramp.

Requirements

Required technical skills and experience:

• 5+ years semiconductor test engineering experience.
• Experience developing ATE test programs (Advantest 93K, Teradyne, or equivalent).
• Solid understanding of DFT methodologies (scan, ATPG, MBIST, LBIST) and memory test techniques.
• Experience debugging silicon issues at the tester and correlating failures to design or process causes.
• Familiarity with advanced CMOS nodes and production test challenges.
• Ability to work effectively in a cross-functional engineering environment.
• May require eligibility checks for UK, US, or other export-control regulations.

Preferred:

• Experience testing AI accelerators, GPUs, networking ASICs, or other high-performance compute ICs.
• Experience with PCIe Gen5/Gen6, LPDDR4/5/6, or other high-speed interfaces.
• Exposure to advanced packaging, chiplets, or multi-die test flows.
• Proven track record of improving yield, reducing test time, or optimizing cost in high-volume manufacturing.

Education Requirements

Not specified.

About the Company

Company: Fractile

Headquarters: London, UK

Fractile is on a mission to revolutionize AI by developing silicon, systems, and software that enable the fastest execution of advanced models at lower costs. Established in 2022, the company has rapidly expanded, fostering a collaborative culture in its London and Bristol offices. With a focus on innovation in ML/AI IC product development, Fractile combines hardware and software to deliver high-impact solutions for data center applications.