Semiconductor Packaging Research Engineer
Intel CorporationJob Title
Semiconductor Packaging Research Engineer
Role Summary
Research and develop advanced semiconductor packaging and heterogeneous integration technologies to evaluate architectures, materials, interconnects, reliability, and manufacturability trade-offs for future products. The role focuses on either packaging process integration or modeling/simulation and works across research, design, process, materials, reliability, manufacturing, suppliers, and academia.
Experience Level
Entry / Early Career - minimum 1+ year of relevant experience in semiconductor packaging research, process integration, modeling/simulation, reliability, materials, or heterogeneous integration.
Responsibilities
Conduct research and produce actionable technical outputs that inform product and development decisions.
- Investigate advanced packaging concepts (chiplets, heterogeneous integration, 2.5D/3DIC, hybrid bonding, interposers, die-to-die interconnects).
- Lead process integration learning or modeling/simulation to assess feasibility, reliability, manufacturability, and technology readiness.
- For process integration: define integration flows, research vehicles, DOE, defect/yield learning, qualification evidence, and risk mitigation.
- For modeling: develop and validate thermal, thermo-mechanical, electrical, reliability, or multi-physics models using experimental and failure-analysis data.
- Translate product needs into research hypotheses, technical plans, reports, IP, publications, and development-transfer inputs.
- Collaborate with cross-functional teams including process, materials, reliability, manufacturing, suppliers, and external partners.
Requirements
Must-have technical experience and demonstrated skills; preferred items listed separately.
- Minimum 1+ year experience in semiconductor packaging research, advanced packaging integration, process integration, modeling/simulation, reliability, materials, or heterogeneous integration.
- Hands-on experience in one or more: process integration, research vehicle execution, DOE, defect/yield learning, qualification, model development & validation, or multi-physics simulation.
- Experience with advanced packaging technologies such as flip chip, chiplets, 2.5D/3DIC, fan-out, hybrid bonding, interposers, HBM integration, advanced substrates, or die-to-die interconnects.
- Ability to convert ambiguous research problems into testable hypotheses, experiments, validation metrics, and actionable recommendations.
- Strong cross-functional communication and documentation skills (reports, technical guidance, development-transfer inputs).
- Nice-to-have: prototype builds, technology readiness assessment, package-system co-optimization, chip-package-board co-design, modeling tool experience (ANSYS, Abaqus, COMSOL, HFSS, Cadence, MATLAB, Python, JMP), and a record of patents/publications.
Education Requirements
Master's or Ph.D. in Mechanical Engineering, Electrical Engineering, Materials Science, Applied Physics, Computational Mechanics, Microelectronics, Semiconductor Manufacturing, or a related technical field. The posting also indicates advanced specialization (Ph.D.) is preferred; equivalent practical experience and relevant industry/internship/school research experience are acceptable.
About the Company
Company: Intel Corporation
Headquarters: Santa Clara, California, USA
Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.
