Semiconductor Packaging Integration Research Manager

Job Title

Semiconductor Packaging Integration Research Manager

Role Summary

Foundry Technology Research seeks a manager to lead advanced packaging integration research that enables next-generation heterogeneous semiconductor systems. The role defines early-stage integration strategies across package architecture, chiplet assembly, substrates/interposers, wafer- and die-level reliability, and manufacturability.

The manager will guide exploratory concepts from hypothesis and feasibility demonstration through prototype learning, technology readiness assessment, and transfer to development or manufacturing teams while coordinating across device, design, materials, process, reliability, testing, manufacturing, suppliers, and academic partners.

Experience Level

Senior. Minimum of 7 years of experience in semiconductor technology roles; management of research programs or multidisciplinary teams expected.

Responsibilities

Lead and coordinate research activities that validate and mature advanced packaging integration concepts.

• Lead packaging integration research programs focused on heterogeneous integration, chiplets, 2.5D/3DIC, hybrid bonding, wafer-level packaging, and emerging die-to-die interconnects.
• Define integration research strategy, technical roadmaps, milestones, and decision criteria aligned to product and system scaling requirements.
• Manage a multidisciplinary team of researchers, integration engineers, modeling experts, and technical program leads.
• Translate system requirements into package integration solutions balancing performance, power, area, latency, bandwidth, thermal behavior, mechanical stress, reliability, cost, and manufacturability.
• Coordinate cross-domain work with silicon design, device, process, substrate, assembly, test, reliability, thermal, signal/power integrity, failure analysis, and manufacturing teams.
• Drive feasibility studies, architecture trade-offs, process evaluations, design rules, prototyping, DOE, and experimental validation.
• Lead technology readiness assessments, risk reviews, failure-analysis learning cycles, and manufacturing feasibility reviews for early-stage options.
• Drive IP generation, technical publications, benchmarking, and knowledge transfer; communicate progress and strategic recommendations to senior leaders.
• Guide research-to-development transfer by defining integration requirements, qualification gaps, process-control needs, and scaling paths.

Requirements

Essential technical leadership skills and domain knowledge. Degree requirements are summarized in the Education Requirements section below.

• Proven experience leading advanced technology research programs, multidisciplinary technical teams, cross-functional initiatives, or external research collaborations.
• Ability to convert ambiguous integration challenges into clear hypotheses, experimental plans, measurable milestones, and actionable recommendations.
• Deep understanding of package-system integration topics: chiplet architectures, advanced interconnects, substrates/interposers, assembly materials, wafer-level processes, thermal-mechanical behavior, power delivery, signal integrity, reliability, and manufacturability trade-offs.
• Strong written and verbal communication skills for presenting complex technical findings and trade-offs to executive and cross-functional audiences.
• Experience managing research portfolios, defining roadmaps, and driving research-to-development transfer and technology readiness assessments.
• Position of Trust: role requires consent to and successful completion of an extended background investigation.

Nice-to-have:

• Track record of innovation (patents, publications, conference presentations) and participation in industry consortia or university collaborations.
• Experience with prototype builds, pathfinding, early manufacturing feasibility, and process-integration learning.
• Knowledge of thermal-mechanical modeling (warpage, stress, CTE mismatch), electromigration, high-speed I/O, power & signal integrity, and package-level co-design.
• Experience partnering with suppliers, OSATs, foundries, equipment vendors, or customer technology teams; familiarity with AI/HPC, data center, automotive, mobile, networking, edge, or advanced memory packaging requirements.

Education Requirements

Master's degree in Electrical Engineering, Mechanical Engineering, Materials Science, Chemical Engineering, Applied Physics, Microelectronics, Semiconductor Manufacturing, or a related engineering/science discipline. Ph.D. preferred. Minimum of 7 years of relevant semiconductor technology experience.

About the Company

Company: Intel Corporation

Headquarters: Santa Clara, California, USA

Intel Corporation is a leading multinational technology company known for its innovative semiconductor solutions, including microprocessors, artificial intelligence accelerators, and memory products. Headquartered in the United States, Intel focuses on cutting-edge technology and a collaborative working environment, driving advancements in semiconductor manufacturing to meet global demands. The company emphasizes professional development and aims to shape the future of technology through groundbreaking designs.