Semiconductor Design Package Engineer

Job Title

Semiconductor Design Package Engineer

Role Summary

Design advanced semiconductor packages (ceramic and organic substrates) including layout, parasitic extraction, and optimization. Work closely with IC/SoC design, SI/PI, and thermal teams to define package requirements and ensure manufacturable, high-performance interposer and substrate solutions.

Experience Level

Senior — typically requires 8 to 10 years of semiconductor packaging design, modeling, and simulation experience.

Responsibilities

Lead package layout, extraction and analysis across electrical and thermal domains and deliver released package designs and documentation.

• Design package layouts using standard CAD tools and generate fabrication artwork.
• Extract package parasitics and perform signal integrity (SI) and power integrity (PI) analysis.
• Collaborate with SoC/IC teams to optimize die floorplans, bump patterns, and stack-ups.
• Design custom interposers and substrates, including 2.5D and 3D package architectures.
• Optimize layouts for SI/PI and manufacturability; address packaging-related thermal issues.
• Document designs and manage releases in the archival system.
• Coordinate with cross-functional teams to validate package-level performance and resolve issues.

Requirements

Must-have skills and tools for the role; preferred items noted.

• 8+ years practical experience in semiconductor package design, modeling, and simulation.
• Strong expertise with Cadence Allegro Package Designer Plus (APD+).
• Experience with interposer and substrate layouts and advanced package technologies.
• Hands-on experience with 2.5D and 3D package design and floorplan/bump optimization.
• Experience extracting parasitics and using SI/PI tools for package-level simulation.
• Familiarity with SI tools (Sigrity) and PI tools (Celsius PowerDC or equivalent).
• Strong problem-solving, written and verbal communication, organization, and cross-team collaboration skills.
• Preferred: RF/microwave EM and circuit simulation tools such as AWR, Momentum, and HFSS.

Education Requirements

Bachelor's degree in Electrical Engineering, Mechanical Engineering, or another semiconductor-packaging-related discipline is required.

About the Company

Company: Retym Israel

Technology company hiring VLSI/ASIC digital design engineers for communication systems and SoC/IP development. Work includes RTL design, verification, synthesis, timing closure, and silicon bring-up.