Semiconductor Design Engineer 5
Cypress HCMJob Title
Semiconductor Design Engineer 5
Role Summary
Design and deliver complex semiconductor IP and chips with an emphasis on IO, clocking, and power-domain interactions. Work across floorplanning, physical/electrical requirements, package and board interfaces, and drive signaling and ESD definitions. Typically leads projects or substantial portions of projects from design through evaluation.
Experience Level
Senior — 10+ years of experience.
Responsibilities
Accountable for engineering, designing, and documenting semiconductor devices and related components.
- Define and design chip IO, clocking schemes, and voltage-domain crossings.
- Create and review floorplans; assess implications for IO and physical/electrical constraints.
- Specify signaling strategies, power-rail and bump-pattern definitions, and ESD requirements.
- Collaborate on package and board design requirements and interfaces.
- Design custom datapaths with a focus on power efficiency.
- Review product requirements and logic diagrams; document specifications and changes.
- Lead or own projects and coordinate with cross-functional teams during implementation and evaluation.
Requirements
Core qualifications and skills required for the role.
- 10+ years of semiconductor design engineering experience.
- Strong background in IO definition, clocking, and voltage-domain crossing.
- Proven experience driving floor-planning and resolving physical/electrical implications for IO design.
- Experience defining signaling, power-rail/bump-pattern, and ESD requirements.
- Familiarity with package and board design interactions.
- Expertise in custom datapath definitions and power-efficient design techniques.
Nice-to-have: Ownership of full-chip delivery and prior cross-functional coordination with package/board teams.
Education Requirements
Not specified.
About the Company
Company: Cypress HCM
A human capital/recruiting firm that posts and fills technical and semiconductor engineering roles, connecting employers with experienced engineering talent.
