RTL-to-GDS Implementation, Senior Principal Solutions Engineer

Job Title

RTL-to-GDS Implementation, Senior Principal Solutions Engineer

Role Summary

Senior Principal Solutions Engineer responsible for supporting customer adoption of Cadence implementation tools and methodologies across RTL-to-GDSII flows. Primary focus on place-and-route, physical synthesis, CTS and STA to help customers meet Design PPA goals and successful tapeouts.

This is a customer-facing role that combines technical delivery, methodology articulation, benchmarking, and training for full-flow implementation projects.

Experience Level

Senior - requires 7+ years of relevant ASIC design and implementation experience.

Responsibilities

Key responsibilities include owning block and top-level implementation efforts and leading customer-focused signoff activities.

• Lead RTL-to-GDSII implementation projects using Cadence tools for complex blocks (CPUs, GPUs, DSPs).
• Perform and debug place-and-route, clock-tree synthesis, and static timing analysis to achieve PPA targets.
• Develop and present implementation methodologies and elevator-level explanations across the Cadence tool portfolio.
• Run and manage customer benchmarks and competitive evaluations to demonstrate technical differentiation.
• Provide tapeout support and collaborate on multi-node, foundry-standard implementations.
• Deliver customer training and full-flow implementation services; broaden product and methodology expertise over time.

Requirements

Must-have skills and experience are listed first; nice-to-have items follow.

• Must-have: 7+ years of ASIC design/implementation experience.
• Must-have: Hands-on ASIC design experience using Verilog or equivalent HDLs.
• Must-have: Deep practical experience with place-and-route/physical synthesis, CTS, and static timing analysis using Cadence or Synopsys tools.
• Must-have: Proven experience supporting RTL-to-GDS implementation flows and signoff activities.
• Nice-to-have: Experience with Encounter Digital Implementation Platform.
• Nice-to-have: Experience with low-power and multi-voltage design techniques.
• Nice-to-have: Experience with competitive benchmarking on complex compute blocks and multi-node implementations.
• Nice-to-have: Tapeout support and clock-tree debugging experience.

Education Requirements

Not specified.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.