RTL Engineer

Job Title

RTL Engineer

Role Summary

Design and implement synthesizable RTL for high-performance microcontroller (MCU) and SoC digital blocks. Work within the MCU product-development team on performance-, power- and timing-sensitive IP and collaborate with verification, EDA, and software teams to deliver pre- and post-silicon validated designs.

Experience Level

Mid-level (5+ years of hands-on RTL design experience)

Responsibilities

Primary responsibilities include designing RTL, ensuring timing/power targets, and collaborating across functional teams:

• Define and implement RTL architecture and coding style for complex SoC blocks.
• Develop and maintain synthesizable SystemVerilog or VHDL for cores, peripherals, interfaces, and DMA logic.
• Create and own RTL simulation and synthesis testbenches and run regression suites to verify functionality and timing.
• Collaborate with verification engineers to ensure coverage, resolve RTL bugs, and support pre-silicon validation.
• Perform timing analysis, develop SDC constraints, and iterate on RTL to meet setup/hold and frequency targets.
• Lead and implement power-aware RTL techniques (clock gating, power domains, voltage/frequency scaling).
• Participate in design reviews and document design decisions, trade-offs, and risks.
• Drive RTL quality by defining coding guidelines, linting policies, and best practices.
• Mentor junior RTL designers and support team ramp-up.
• Work with EDA teams to evaluate and integrate synthesis, place-and-route, and STA tools.
• Support post-silicon bring-up and debug, assisting firmware and ROM teams with RTL-related issues.

Requirements

Must-have:

• 5+ years hands-on RTL design experience on high-performance SoCs (preferably MCUs or wireless connectivity devices).
• Strong proficiency in SystemVerilog or VHDL; ability to write clean, synthesizable, testable RTL.
• Deep knowledge of digital design fundamentals: pipelining, state-machine design, bus protocols (AHB/APB/AXI), FIFOs, arbitration, and clock-domain crossing.
• Experience with synthesis tools (for example Design Compiler, Innovus) and static timing analysis; proven ability to meet performance and power targets.
• Proven low-power RTL techniques such as clock gating, power-domain isolation, and dynamic voltage/frequency scaling.
• Familiarity with verification flows (UVM, simulation, coverage) to collaborate effectively with DV teams.
• Advanced scripting/automation skills (Tcl, Perl, Python, Bash) for flow automation and CI/CD integration.
• Strong written and verbal communication and stakeholder-management skills across global teams.
• Demonstrated ability to lead design efforts, meet schedules, and mentor junior engineers.

Nice-to-have:

• Experience defining RTL architecture and clocking strategies for complex SoCs.
• Hands-on experience with SDC development and timing closure workflows.
• Experience working with EDA teams to evaluate and integrate new tools and flows.
• Prior involvement in post-silicon bring-up and performance tuning.

Education Requirements

B.S. (or M.S.) in Electrical, Electronics, Computer Engineering or a related technical discipline (Bachelor's degree listed as the required level).

About the Company

Company: Texas Instruments

Headquarters: Dallas, Texas, USA

Texas Instruments is a global semiconductor company that designs, manufactures, and sells analog and embedded processing chips for various markets including industrial, automotive, and personal electronics. The company's innovations aim to make electronics more affordable and reliable, fostering advancements in technology through each generation of semiconductors.