RTL Design (Turing - AI/ML) - Senior Engineer / Senior Lead
QualcommJob Title
RTL Design (Turing - AI/ML) - Senior Engineer / Senior Lead
Role Summary
Design and implement RTL for AI/ML subsystems, working closely with product definition and architecture teams. Lead or contribute to microarchitecture, RTL coding, integration, and verification activities to meet performance, power, area and schedule (PPAS) targets.
Collaborate with synthesis, power, DFT, PD and system teams to deliver block-level design collateral (timing constraints, UPF, assertions) and resolve integration issues.
Experience Level
Senior. The role expects experienced RTL/hardware engineers; minimum qualifications reference experience levels starting at 1–3+ years depending on degree (see Education Requirements for details).
Responsibilities
Accountabilities include microarchitecture-to-implementation work, RTL delivery, verification support, and cross-team coordination.
- Define block-level design (block diagrams, interfaces, clocking, transaction flow, pipelines, low-power strategy).
- Develop microarchitecture and RTL coding strategies to meet PPAS goals for subsystems/SOC integration.
- Lead and mentor engineers on RTL implementation, function/performance simulation and debug.
- Drive lint, CDC, formal/FV, and UPF checks to ensure design quality and signoff readiness.
- Implement assertions and white-box testing to improve coverage and debug efficiency.
- Coordinate with synthesis, power, DFT, PD, and system teams on use cases, power, timing and datapath interactions.
- Size performance parameters (bandwidth, latency, bus transactions) across voltage/frequency corners.
Requirements
Core technical skills and domain experience required; education and degree-related experience are summarized in Education Requirements below.
- Proven RTL implementation experience with Verilog/SystemVerilog and strong waveform/simulator debugging skills.
- Solid understanding of low-power microarchitecture techniques and AI/ML system design trade-offs.
- Thorough knowledge of computer/microarchitecture design, including high-performance design techniques.
- Familiarity with NoC design principles and performance/transaction sizing.
- Experience driving Lint, CDC, functional verification (FV), and UPF flows.
- Experience developing assertions and white-box test strategies.
- Ability to work with synthesis, power, DFT and PD teams on integration and collateral exchanges.
- Experience leading technical teams and coordinating across stakeholders to deliver design collateral.
- Nice-to-have: prior work on AI/ML accelerator blocks or high-performance compute subsystems.
Education Requirements
Required: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field (with 3+ years hardware engineering experience), OR Master's degree in those fields (with 2+ years experience), OR PhD in those fields (with 1+ year experience). Equivalent practical experience accepted where specified.
About the Company
Company: Qualcomm
Headquarters: San Diego, California, United States
Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.
