RTL Design Lead / IC Front-End Architect / Datapath Lead

Job Title

RTL Design Lead / IC Front-End Architect / Datapath Lead

Role Summary

Lead the front-end micro-architecture and own the high-speed datapath for a first-of-its-kind chiplet in a startup building photonics infrastructure. This is a founding-hire technical leadership role responsible for architecture, coding and CDC standards, and enabling verification and physical closure.

Experience Level

Senior — requires 10+ years of digital design and micro-architecture experience with lead ownership of a high-throughput datapath or SerDes-adjacent SoC.

Responsibilities

Define architecture, implementation standards, and ownership boundaries for the front-end and datapath; collaborate with DV, backend, DFT, and modelling leads and grow the front-end team.

• Define front-end micro-architecture, block partitioning, and the specification RTL implements.
• Establish RTL coding standards, lint rules, CDC/RDC signoff flow, and clean-RTL policy.
• Design and own the high-speed datapath: per-lane alignment/deskew/mux, elastic FIFOs, and adapter logic between UCIe and the optical front end.
• Specify transport/link framing, mapping, and adaptation logic.
• Drive timing- and floorplan-aware micro-architecture (pipelining, retiming, partitioning) for multi-hundred-Gbps physical closure.
• Define clocking, reset, and low-power architecture including domain strategy and UPF intent.
• Establish designer-level verification practices: block testbenches, sanity checks, and SVA coverage before DV handoff.
• Architect DFT and on-die observability/controllability for a die that is difficult to probe.
• Set IP integration, interface/register conventions, and parameterization for scalable configurations.
• Lead, mentor, and grow the front-end design team.

Requirements

Must-have technical experience and proven ownership in front-end datapath architecture and delivery.

• 10+ years in digital design and micro-architecture with lead ownership of a high-throughput datapath or SerDes-adjacent SoC.
• Experience designing datapaths for network switches/NICs or memory controllers (or equivalent high-throughput, high-reliability datapaths).
• Strong SystemVerilog RTL skills and timing-aware micro-architecture at multi-hundred-Gbps aggregate rates; disciplined CDC practice.
• Working command of UCIe/PCIe/CXL datapath concepts and high-speed lane alignment/deskew techniques.
• Proven ownership of front-end design methodology: lint, CDC/RDC signoff, clocking/reset architecture, and collaboration for DFT and physical closure.
• Track record of translating system requirements into implementable, verifiable architecture specifications.

• Direct UCIe or chiplet die-to-die interface architecture experience (PCIe/CXL/CHI familiarity).
• FEC/coding datapath experience (e.g., Reed–Solomon) or gray-code mapping knowledge.
• Optical transceiver, co-packaged optics (CPO), linear-drive optics background or advanced-node (N5/N3/N2) implementation experience.

Education Requirements

Not specified.

About the Company

Company: Lumilens

Headquarters: San Jose, CA, USA

Lumilens develops integrated photonics and optical interconnect solutions for high-speed data communication and chip-to-chip interfaces, focusing on optical front-end hardware and co-packaged optics for advanced semiconductor systems.