RTL Design Engineers

Job Title

RTL Design Engineers

Role Summary

Contract positions for senior digital chip design and verification engineers to support an AI evaluation program focused on frontier silicon and chip-design workflows. Two parallel tracks are hiring: RTL Design Engineer and Design Verification Engineer.

Remote (USA and Canada only). Target engagement ~3+ months starting the week of 04/23. Full-time preferred; high availability expected (≈40 hours/week).

Experience Level

Senior; 3–10 years of relevant digital RTL or design verification experience (the posting requests senior contributors able to commit meaningful time).

Responsibilities

Primary responsibilities vary by track. Work will focus on RTL development, verification infrastructure, debug, and cross-team collaboration.

• Develop synthesizable RTL in Verilog/SystemVerilog and implement digital structures (FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains).
• Design and maintain reusable verification components, UVM testbenches, constrained-random tests, and coverage-driven regressions (DV track).
• Run and interpret simulation, waveform debug, lint, synthesis, timing analysis, CDC checks, and DFT-aware design flows.
• Debug RTL and verification failures using simulation logs and waveform viewers; drive root-cause analysis and fixes.
• Write clear design and verification documentation, plans, and debug reports; communicate technical tradeoffs to cross-functional teams.
• Collaborate with architects, implementation, and verification teams to integrate IP and close coverage/timing gaps.
• Leverage EDA tools and LLM-based tools to accelerate development, test generation, debugging, and documentation workflows.
• Integrate and validate bus/protocol interfaces (e.g., AMBA) and verification IP where applicable.

Requirements

Must-have qualifications (track-specific details noted):

• 3–10 years of hands-on experience in digital RTL design or design verification (aligned to the chosen track).
• Strong proficiency in Verilog/SystemVerilog. SystemVerilog + UVM required for the Design Verification track.
• Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, and common bus protocols.
• Practical experience with ASIC design flows and EDA tools for simulation, waveform debug, linting, synthesis, timing analysis, CDC, and DFT-aware design.
• Experience developing reusable verification components, scoreboards, functional coverage, assertions (SVA), and achieving coverage closure (DV track).
• Ability to write clear technical documentation, verification plans, and debug reports; effective cross-team communication skills.

Preferred / Nice-to-have:

• Experience with AMBA protocols (AXI, AHB, APB).
• Background in CPU, GPU/ML accelerators, networking, memory subsystems, PCIe/high-speed IO, SoC interconnects, or low-power design/verification.
• Exposure to formal verification methods, SV/UVM-based verification flows, reusable VIP, scoreboards, and coverage-driven regression infrastructure.

Education Requirements

Not specified.

About the Company

Company: Naviesto

Technology recruitment platform connecting engineering and technical talent with contract and remote roles, often focused on specialized areas like chip design and verification.