RTL Design Engineer - Wireless SoC

Job Title

RTL Design Engineer - Wireless SoC

Role Summary

Design and implement RTL for high-performance digital blocks in next-generation wireless SoCs. Collaborate with architecture, analog/mixed-signal (AMS), verification, and physical design teams to deliver production-quality silicon.

Experience Level

Mid-level. Years of experience: Not specified.

Responsibilities

Primary responsibilities include:

• Design and implement RTL (SystemVerilog/Verilog) for digital IP and SoC subsystems.
• Optimize designs for area, power, and timing; ensure synthesizable and testable RTL.
• Collaborate with architecture, AMS, verification, and physical design teams during design and integration.
• Participate in design and code reviews, and contribute to integration and system-level verification.
• Support silicon bring-up, characterization, and post-silicon debug.
• Produce and maintain design documentation and verification collateral.

Requirements

Must-have and preferred qualifications:

• Must-have: Practical RTL design experience using SystemVerilog or Verilog; RTL synthesis and timing-closure experience; experience working on SoC components and collaborating with verification and AMS teams.
• Must-have: Familiarity with EDA tools for simulation, synthesis, and linting; ability to interpret timing reports and constraints.
• Nice-to-have: Experience with wireless protocols (e.g., LTE/5G), DSP blocks, FPGA prototyping, or UVM-based verification.
• Nice-to-have: Scripting skills (Python, Tcl) and prior involvement in silicon bring-up and characterization.

Education Requirements

Not specified.

About the Company

Company: Purple Hires