RTL Design Engineer, Staff Level - SoC Design

Job Title

RTL Design Engineer, Staff Level - SoC Design

Role Summary

Join the System Solutions Group to produce signoff-quality RTL and timing constraint packages for customer SoC projects. The role focuses on RTL quality signoff, constraint development, preliminary synthesis checks, formal equivalence, and integration of third-party IP into subsystems and full SoCs.

This position works directly with architecture, verification, and implementation teams to reduce downstream respins and deliver synthesis-ready RTL for production tape-outs.

Experience Level

Senior level. Typical guidance: 4+ years of hands-on experience in RTL design, verification, or SoC integration.

Responsibilities

Deliver RTL signoff and constraints that enable clean, synthesis-ready handoffs to implementation teams. Key responsibilities include:

• Run Spyglass (or equivalent) for LINT, CDC, and RDC checks across IP blocks, subsystems, and full SoCs.
• Develop and validate SDC timing constraints for synthesis and static timing analysis that capture design intent.
• Execute preliminary synthesis runs (Design Compiler or similar) to verify RTL synthesizability and identify timing bottlenecks.
• Perform formal equivalence checking between RTL and gate-level netlists using Formality or equivalent tools.
• Integrate customer and third-party IP into subsystem and SoC RTL, managing hierarchy, interfaces, and DFT concerns.
• Debug and resolve CDC, reset-domain, and RTL coding issues in collaboration with architecture and verification teams.
• Deliver signoff-quality RTL and constraint packages to implementation teams on customer projects.

Requirements

Must-have technical skills and experience for immediate contribution:

• 4+ years of hands-on experience in RTL design, verification, or SoC integration.
• Proven experience using Spyglass or equivalent tools for LINT, CDC, and RDC static verification.
• Strong working knowledge of SDC timing constraint development and synthesis flows; experience with Design Compiler or similar tools.
• Solid understanding of clock domain crossing, reset domain crossing, and common RTL design pitfalls affecting timing and functionality.
• Experience running formal equivalence checking with Formality or equivalent tools; familiarity with SystemVerilog/Verilog RTL coding.
• Experience integrating third-party IP and managing subsystem-to-SoC hierarchy and interfaces.
• Ability to debug synthesis mismatches and determine whether issues are coding-style, tool limitations, or functional bugs.
• Comfort working across time zones and collaborating directly with customer engineering teams.

Education Requirements

Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or a related technical field.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.