RTL Design Engineer, Sr Lead

Job Title

RTL Design Engineer, Sr Lead

Role Summary

Senior RTL design engineer responsible for front-end ASIC/SoC micro-architecture, RTL implementation, and quality signoff for block-level and subsystem designs. The role works closely with architecture, verification, DFT, synthesis/timing, and physical design teams to deliver silicon-ready RTL.

Experience Level

Senior — typically 5+ years of experience in ASIC/SoC front-end design (posting indicates 5+ years preferred).

Responsibilities

Primary responsibilities include translating architecture into synthesizable RTL and ensuring design quality through reviews and signoff activities.

• Develop detailed micro-architecture specifications from high-level requirements.
• Design and implement synthesizable RTL using Verilog/SystemVerilog.
• Perform RTL quality checks: lint analysis and cleanup, CDC/RDC analysis and closure, FSM and structural checks.
• Participate in design reviews and enforce coding guidelines.
• Develop and maintain micro-architecture and interface documentation.
• Work with verification teams to define verification plans and resolve functional issues.
• Support synthesis, timing analysis, and timing closure; develop and review SDC constraints for block and subsystem designs.
• Analyze and debug issues across simulation, synthesis, and implementation stages.
• Collaborate with DFT and physical design teams for integration and tapeout.

Requirements

Must-have:

• 5+ years experience in ASIC/SoC front-end RTL design (experience requirement noted in posting).
• Hands-on RTL design using Verilog/SystemVerilog and strong digital design fundamentals.
• Micro-architecture definition and documentation skills.
• Experience with lint tools (e.g., SpyGlass, Questa Lint) and CDC tools (e.g., SpyGlass CDC, Questa CDC) for signoff.
• Understanding of clocking architectures, reset strategies, and low-power design concepts.
• Experience debugging RTL and simulation issues across design stages.
• Ability to develop and review SDC constraints and support timing closure activities.
• Strong analytical, communication, and cross-team collaboration skills.

Nice-to-have / Preferred:

• Experience with synthesis flows (Design Compiler, Genus, or equivalent) and timing analysis concepts (setup/hold, CDC, timing closure).
• Exposure to DFT methodologies and low-power formats (UPF/CPF).
• Experience with complex SoC/IP development (CPU, DSP, AI/ML, networking, multimedia, connectivity).
• Scripting for automation (Python, Perl, TCL).

Education Requirements

Posting requires a Bachelor's, Master's, or PhD in Computer Science, Electrical/Electronics Engineering, Computer Engineering, or a related engineering field. The job explicitly allows equivalent combinations of degree and experience (e.g., Bachelor + 3+ years, Master + 2+ years, PhD + 1+ year) as alternatives to strict degree requirements.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.