RTL Design Engineer (Peripheral) - Sr Lead

Job Title

RTL Design Engineer (Peripheral) - Sr Lead

Role Summary

Senior RTL design engineer responsible for end-to-end design and microarchitecture of peripheral IP blocks within the hardware engineering team. Own one or more peripheral IP projects, coordinate across SoC teams, and drive design to implementation.

Role includes technical leadership, mentoring junior engineers, and collaboration with verification, validation and cross-functional teams for pre/post-silicon debug.

Experience Level

Senior. Typical experience: 8–10 years in ASIC IP core design. Minimum qualifications also list alternative experience bands tied to degree (see Education Requirements).

Responsibilities

Key responsibilities include:

• Design and microarchitect peripheral IPs and deliver RTL to meet specification and timing goals.
• Define microarchitecture and implementation approach for assigned IP(s).
• Drive projects independently from specification through handoff; provide schedule estimates and meet milestones.
• Coordinate and resolve cross-team dependencies with verification, validation, and other SoC teams.
• Mentor and guide junior engineers; lead a small design team when required.
• Work with verification and validation teams on pre- and post-silicon debug and root-cause analysis.

Requirements

Must-have and preferred technical skills and experience.

• Must-have: 8–10 years of hands-on ASIC IP core design experience with proven RTL design and microarchitecting skills.
• Must-have: Hands-on experience with low-power design techniques.
• Must-have: Strong experience with multi-clock designs and asynchronous interfaces.
• Must-have: Proficiency with ASIC development tools such as lint, CDC analysis, synthesis (Design Compiler) and timing analysis (PrimeTime).
• Must-have: Strong problem solving, communication, and teamwork; able to work with minimal supervision.
• Nice-to-have: Knowledge of AMBA protocols (AXI, AHB, APB) and familiarity with peripherals (USB, PCIe, Ethernet) and SoC clock/reset/debug architecture.
• Nice-to-have: Experience with constraint development, timing closure, and synthesis-related timing concepts.
• Nice-to-have: Familiarity with SystemVerilog/Verilog; experience with C/C++, Perl, or Python is a plus.
• Nice-to-have: People management experience and prior responsibility for driving multiple projects.

Education Requirements

Required: Bachelor's degree in Electrical/Electronics Engineering, Computer Science, Engineering, or a related field (or equivalent). Preferred: Master’s degree. The posting also allows alternative qualification/experience combinations: Bachelor's + 4+ years relevant experience, Master’s + 3+ years, or PhD + 2+ years in Hardware Engineering or related work.

About the Company

Company: Qualcomm

Headquarters: San Diego, California, United States

Qualcomm is a global leader in semiconductor and telecommunications equipment, specializing in mobile technologies and innovations. Known for its Adreno GPUs, the company provides solutions enabling advancements in mobile gaming, AI, VR/AR, and autonomous driving. Qualcomm's cutting-edge technology and commitment to high-performance, power-efficient designs drive the evolution of mobile graphics and connectivity worldwide.